Current-Mode ADC Architecture for Low-Power High-Resolution Sensing

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Solution Overview

Problem

Prior art analog to digital converters (ADCs) are highly consumptive of power and provide relatively low resolution, making them unsuitable for applications with limited power budgets and requiring high performance.

Innovation Solution

The development of novel ADC designs and architectures that enable high-resolution digital format data conversion with simultaneous drive and sense capabilities, utilizing a single line for both driving and sensing analog signals, and incorporating non-linear N-bit digital to analog converters (DACs) for efficient power management and broad dynamic range sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If prior art ADC designs are used, then device complexity is reduced, but power consumption is high and resolution is low

Engineering Contradiction:
ImproveresolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The ADC is divided into multiple parallel sub-ADCs (first and second ADCs) that operate simultaneously on different segments of the input signal range. Each sub-ADC handles a portion of the dynamic range, allowing for higher overall resolution through digital combination of the segmented results, while each individual sub-ADC can be designed to consume less power.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a time dimension by using multiple ADCs operating in parallel to process different signal segments simultaneously. This dimensional approach allows the system to achieve high resolution without requiring a single high-power ADC, effectively trading temporal processing for reduced instantaneous power consumption.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If prior art ADC designs are used, then device complexity is reduced, but measurement precision is low

Engineering Contradiction:
ImproveresolutionVSAvoidarchitecture complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The input signal range is segmented into multiple portions, with each portion processed by a dedicated sub-ADC. The digital outputs from these sub-ADCs are then combined through digital processing to achieve high-resolution conversion. This segmentation allows each sub-ADC to be simpler while the collective system achieves high precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A digital processing unit acts as an intermediary that combines the outputs from multiple low-resolution sub-ADCs to produce a high-resolution digital output. This intermediary digital processing stage enables the system to achieve high measurement precision without requiring each individual ADC component to be complex.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If high-resolution conversion is achieved, then measurement precision is improved, but power consumption increases

Engineering Contradiction:
ImproveresolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The conversion process is segmented across multiple parallel ADC paths, each handling a specific dynamic range segment. This allows the system to achieve high resolution through the combination of multiple lower-power conversions rather than relying on a single high-power high-resolution ADC.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses periodic switching between different ADC paths based on the input signal amplitude. By periodically selecting which sub-ADC to use based on the current signal segment, the system maintains high resolution while managing power consumption through selective activation of processing paths.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10862492B1Current operative analog to digital converter (ADC)
Publication Date: 2020.12.08 SIGMASENSE LLC
  • US10862492B1 patent drawing
  • US10862492B1 patent drawing
  • US10862492B1 patent drawing

AI summary

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).