Current-Mode Analog Multipliers for Low-Power Asynchronous AI MACs
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Solution Overview
Problem
Current analog and mixed-signal current-mode multipliers and multiply-accumulate circuits face challenges in achieving small size, low cost, low current consumption, asynchronous operation, reduced dynamic power consumption, and compatibility with mainstream CMOS fabrication, while maintaining accuracy and reducing noise and latency in AI and ML applications.
Innovation Solution
The development of mixed-signal multi-quadrant data converters and multipliers that operate in current mode, utilizing single-quadrant multipliers and polarity conditioning circuits, eliminate the need for resistors and capacitors, and leverage substrate BJTs to achieve low power consumption and asynchronous operation, with designs optimized for low power supplies and subthreshold region operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional analog multipliers are used, then multiplication function is achieved, but device size and manufacturing cost increase
Solution Approach 1:
The patent segments the multiplier function into distinct operational quadrants (first, second, third, fourth quadrants) that can be independently controlled through polarity conditioning circuits. This segmentation allows the use of simpler single-quadrant multiplier cores while achieving full multi-quadrant functionality through modular polarity management, reducing overall circuit complexity and manufacturing cost
Solution Approach 2:
The patent introduces polarity conditioning circuits as intermediary components that condition the input signals before they reach the multiplier core. These conditioning circuits manage the polarity of inputs to ensure proper operation across all four quadrants, enabling the use of simpler multiplier architectures and reducing the need for complex internal circuitry within the multiplier itself
2Use of energy by moving object
If conventional analog multipliers with resistors and capacitors are used, then accurate computation is achieved, but current consumption and power supply requirements increase
Solution Approach 1:
The patent extracts and removes the resistors and capacitors from the multiplier circuit, replacing them with current-mode operational elements. This extraction eliminates the need for high power supply voltages required by traditional RC-based analog multipliers, significantly reducing current consumption while maintaining computation accuracy through current-mode signal processing
Solution Approach 2:
The patent substitutes the traditional voltage-mode operation with current-mode operation, replacing voltage-based computation mechanisms with current-based mechanisms. This substitution enables operation at lower power supply voltages and reduces dynamic power consumption while maintaining the mathematical accuracy of multiplication and accumulate operations
3Device complexity
If asynchronous operation is implemented, then clock-free operation and reduced noise are achieved, but circuit complexity increases
Solution Approach 1:
The patent implements self-service mechanisms where the polarity conditioning circuits automatically adjust signal polarities and the current-mode circuits naturally operate without external clock signals. The circuit self-regulates its operation through the inherent properties of current-mode logic and polarity management, eliminating the need for complex clock distribution networks and reducing dynamic power consumption associated with clocked operation
Data Source
AI summary
Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.