Current-Mode Compute-in-Memory MAC for Low-Power BNN Edge AI
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Solution Overview
Problem
Current machine learning ICs for edge devices and sensors face challenges with high power consumption, latency, cost, and manufacturing complexity, making them unsuitable for cost-sensitive, mass-market applications and requiring local computation for safety and privacy reasons.
Innovation Solution
The development of mixed-signal ICs for binarized neural networks that operate with low power supply voltage, minimal latency, and low dynamic power consumption, using current-mode signal processing and in-memory compute capabilities, and are manufacturable on low-cost CMOS fabrication, eliminating the need for passive resistors and capacitors, and allowing asynchronous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital computation engines are used for machine learning, then computation precision and speed are improved, but power consumption and cost increase
Solution Approach 1:
The patent replaces digital voltage-mode computation with analog current-mode computation. Current-mode MAC units perform multiply-accumulate operations using current mirrors and summing nodes, eliminating the need for expensive deep sub-micron digital circuits while reducing power consumption and enabling edge device deployment
Solution Approach 2:
The patent changes the fundamental computation parameter from voltage (digital) to current (analog). By using current-mode signal processing with binary-weighted current sources and summing nodes, the system achieves efficient MAC operations suitable for binarized neural networks, reducing both power consumption and manufacturing cost
2Manufacturing precision
If advanced deep sub-micron manufacturing is used, then computation precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent adopts shallow sub-micron CMOS fabrication instead of expensive deep sub-micron processes. The analog current-mode circuits are designed to be tolerant of process variations, enabling manufacturing on standard, low-cost CMOS lines with shorter life cycles appropriate for edge devices and mass-market applications
Solution Approach 2:
The patent transitions from voltage-mode digital computation requiring high precision to current-mode analog computation that is inherently more tolerant of process variations. Current mirrors and binary-weighted current sources maintain adequate precision without requiring advanced manufacturing, reducing tooling and wafer costs
3Productivity
If cloud-based machine learning is used, then computation capability is improved, but latency and security risks increase
Solution Approach 1:
The patent enables local computation by implementing MAC units directly on edge devices and sensors. By segmenting the computation function from centralized cloud processing to distributed edge processing, the system eliminates cloud access latency and enables real-time inference while maintaining security and privacy
Solution Approach 2:
The patent empowers edge devices with self-contained machine learning capability through local MAC units. Devices perform binarized neural network inference independently without requiring cloud connectivity, achieving autonomous computation for time-sensitive applications while reducing security risks associated with data transmission
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These ICs enable efficient, low-cost, and secure machine learning on edge devices with reduced latency and power consumption, suitable for mass-market applications, while maintaining performance and reliability.
Implementation Method 1
utilizing digital-to-analog current-mode signal processing in integrated circuits
Data Source
AI summary
Methods of performing mixed-signal current-mode multiply-accumulate (MAC) operations for binarized neural networks in an integrated circuit are described in this disclosure. While digital machine learning circuits are fast, scalable, and programmable, they typically require bleeding-edge deep sub-micron manufacturing, consume high currents, and they reside in the cloud, which can exhibit long latency, and not meet private and safety requirements of some applications. Digital machine learning circuits also tend to be pricy given that machine learning digital chips typically require expensive tooling and wafer fabrication associated with advanced bleeding-edge deep sub-micron semiconductor manufacturing. This disclosure utilizes mixed-signal current mode signal processing for machine learning binarized neural networks (BNN), including Compute-In-Memory (CIM), which can enable on-or-near-device machine learning and or on sensor machine learning chips to operate more privately, more securely, with low power and low latency, asynchronously, and be manufacturable on non-advanced standard sub-micron fabrication (with node portability), that are more mature and rugged with lower costs. An example of enabling features of this disclosure is as follows: to save power in an “always-on’ setting, reduce chip costs, process signals asynchronously, and reduce dynamic power consumption. Current mode signal processing is utilized in combination with CIM (to further reduce dynamic power consumption associated with read/write cycles in and out of memory) for bitwise counting of plurality of logic state ‘1’ of plurality of XOR outputs for MAC arithmetic in BNNs.