Current-Mode Clock Distribution for Low-Power Noise-Resistant VLSI

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Solution Overview

Problem

Current voltage-mode clock distribution networks in VLSI circuits consume high power, limiting performance and battery life in portable electronic systems, and prior art current-mode logic schemes face issues with power consumption and reliability.

Innovation Solution

Implementing current-mode logic switched clock distribution networks using CM logic operated flip-flops and a voltage-mode to current-mode converter for efficient clock signal distribution, reducing dynamic power use and improving noise immunity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If voltage-mode clock distribution networks are used, then clock signal distribution is achieved, but dynamic power consumption is high

Engineering Contradiction:

Improvedynamic power consumptionVSAvoidnoise immunity

Core Design Contradiction:

Use of energy by stationary objectVSReliability

Solution Approach 1:

The patent changes the fundamental operating parameter of clock distribution from voltage-mode to current-mode logic. Current-mode logic uses current signals instead of voltage signals, which fundamentally alters the power consumption characteristics and noise immunity properties of the clock distribution network

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes voltage-mode switching mechanisms with current-mode switching mechanisms. This replacement involves using current-controlled devices and current signal transmission instead of voltage-controlled devices and voltage signal transmission, thereby reducing dynamic power consumption while maintaining or improving noise immunity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Use of energy by stationary object

If device density is increased to reduce interconnect lengths, then power consumption is reduced, but clock speed increases which increases power consumption

Engineering Contradiction:

Improvepower consumptionVSAvoidclock speed

Core Design Contradiction:

Use of energy by stationary objectVSSpeed

Solution Approach 1:

The patent changes the signaling parameter from voltage to current, which alters the power-speed relationship. Current-mode logic enables higher clock speeds with lower power consumption because current signals have lower impedance and can be switched faster with less energy dissipation compared to voltage-mode logic

Inventive Principle:

Principle #35Parameter changes

3Use of energy by stationary object

If voltage swing is minimized to reduce power consumption, then power is reduced, but noise immunity deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidnoise susceptibility

Core Design Contradiction:

Use of energy by stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent substitutes voltage-based signaling with current-based signaling. Current-mode logic inherently provides better noise immunity because current signals are less susceptible to voltage noise and interference, allowing for minimized voltage swings while maintaining robust noise immunity through the use of differential current signaling

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP3100361B1Current-mode clock distribution

Publication Date: 2022.03.09 GUTHAUS MATTHEW

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AI summary

Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.