Current-Mode DFPLL Architecture for Low-Jitter Clock Locking
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Solution Overview
Problem
Conventional digital phase locked loops (PLLs) face challenges with high power consumption, large area occupation, and high jitter performance due to the need for large loop gain factors, complex time-to-digital converters, and high-speed voltage domain components, which limit their stability and bandwidth controllability.
Innovation Solution
A digital fractional phase locked loop (DFPLL) with a current mode low pass filter, utilizing a binary phase frequency detector, current mode low pass filter, and current controlled oscillator, which simplifies the architecture by using current mode DACs and current mirrors for filtering and oscillation, reducing power consumption and area requirements while improving linearity and bandwidth control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional digital PLLs use large loop gain factors to guarantee loop stability and achieve high bandwidths, then loop stability and bandwidth are improved, but quantization noise and jitter performance deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameters of the PLL by using a current-mode architecture instead of voltage-mode, and by employing a TDC with 1fs resolution. This allows achieving loop stability and high bandwidth without requiring large loop gain factors, thereby reducing quantization noise and jitter while maintaining the desired stability and bandwidth characteristics
2Measurement precision
If TDCs are used as the phase detector in digital PLLs to improve performance, then phase detection accuracy is improved, but power consumption and area increase significantly
Solution Approach 1:
The patent implements a simplified TDC architecture that uses disposable, simple circuit elements rather than complex, high-performance components. The TDC is built using basic logic elements and flip-flops that consume minimal power and occupy small area, while still achieving the required 1fs resolution for accurate phase detection
3Reliability
If conventional low pass filters use complex voltage domain adders, multipliers, and DACs, then filtering functionality is achieved, but power consumption and area increase
Solution Approach 1:
The patent substitutes the conventional voltage-domain low pass filter architecture with a current-mode implementation. This replacement eliminates the need for complex voltage domain adders, multipliers, and DACs, while maintaining the essential filtering functionality through current-mode circuitry that is inherently simpler and more power-efficient
4Ease of operation
If digital voltage-controlled oscillators are used to generate control signals, then digital control is achieved, but non-linearity increases and frequency resolution decreases
Solution Approach 1:
The patent changes the control parameter domain from voltage to current by using a current-controlled oscillator (CCO). This allows maintaining digital control capabilities while achieving superior linearity and frequency resolution, as the CCO responds more linearly to control inputs and provides finer frequency tuning steps compared to digital voltage-controlled oscillators
Data Source
AI summary
Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.