Current-Mode Fractional PLL for Low Jitter and Lower Power
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Solution Overview
Problem
Conventional digital phase locked loops (PLLs) face challenges with high power consumption, large area occupation, and high jitter performance due to the need for large loop gain factors, complex time-to-digital converters, and non-linear voltage-controlled oscillators, which limit their bandwidth controllability and resolution.
Innovation Solution
A digital fractional phase locked loop (DFPLL) with a current mode low pass filter, utilizing a binary phase frequency detector, current mode low pass filter, and current controlled oscillator, which simplifies the architecture by eliminating complex voltage domain components and using current mode DACs and current mirrors for efficient noise filtering and power regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional digital PLLs use complex voltage domain components (voltage domain adders, multipliers, DACs), then the PLL can achieve frequency control, but the power consumption and area occupation increase significantly
Solution Approach 1:
The patent replaces the voltage domain control system with a current domain control system. Specifically, voltage domain adders, multipliers, and DACs are substituted with current mode low pass filter components including current adders, current multipliers, and current-to-voltage converters. This substitution leverages the natural current-mode operation of CMOS circuits to achieve the same control function with reduced power consumption and simplified architecture
Solution Approach 2:
The patent changes the operating domain parameter from voltage to current. By operating the PLL control loop in the current domain rather than voltage domain, the system achieves better power efficiency. The current mode low pass filter uses current signals throughout the control path, and only converts to voltage at the final actuation stage, optimizing the overall power consumption profile
2Speed
If digital PLLs use large loop gain factors to guarantee loop stability and achieve high bandwidths, then the PLL bandwidth increases, but quantization noise and jitter performance deteriorate
Solution Approach 1:
The patent changes the domain of operation from voltage to current in the loop filter, which fundamentally alters the noise characteristics. Current mode operation provides better signal-to-noise ratio because current signals are less susceptible to quantization effects and thermal noise compared to voltage signals at the same power level. This enables achieving high bandwidth with lower jitter
Solution Approach 2:
The patent implements current mode versions of all control loop components (current adders, current multipliers, current integrators) that replicate the functionality of conventional voltage domain components but with superior noise performance. The current mode architecture copies the control logic while improving the signal quality throughout the loop
3Adaptability or versatility
If conventional digital PLLs use voltage domain low pass filters with multipliers and DACs, then the filter can control the loop bandwidth, but the area occupation and power consumption increase
Solution Approach 1:
The patent substitutes voltage domain filter components with current mode equivalents. The current mode low pass filter uses current adders, current multipliers, and current integrators that occupy less area and consume less power than their voltage domain counterparts. The current mode architecture eliminates the need for high-speed voltage domain DACs and reduces the complexity of the control signal path
Solution Approach 2:
The patent segments the control loop into distinct current mode functional blocks (current adder, current multiplier, current integrator) that can be independently optimized. Each block processes current signals and passes current signals to the next block, maintaining current mode operation throughout and minimizing the need for voltage conversion stages
4Ease of operation
If digital PLLs use digital voltage-controlled oscillators to generate control signals, then the oscillator can be controlled digitally, but the frequency resolution and linearity are limited
Solution Approach 1:
The patent replaces the digital voltage-controlled oscillator with a current-controlled oscillator. The current mode low pass filter outputs a current control signal that directly controls the oscillation frequency without requiring voltage-to-current conversion. This current mode approach provides finer frequency resolution and better linearity because current control is more direct and less susceptible to quantization effects
Solution Approach 2:
The patent introduces a current mode interface as an intermediary between the digital control logic and the oscillator. Instead of directly controlling the oscillator voltage, the system uses current mode signal processing throughout the control loop, with the current control signal serving as the intermediary that provides precise and linear frequency control
Data Source
AI summary
Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.