Current-Mode Logic Circuit With Integrated Voltage Reset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current mode logic circuits face challenges with high parasitic capacitance and reduced operating speed due to separate reset circuits, which affect the time constant of the RC circuit and increase circuit complexity.
Innovation Solution
The proposed current mode logic circuit employs a voltage sampling circuit with switches and capacitors to integrate and reset output voltage in a direction opposite to the input voltage integration, eliminating the need for a separate reset circuit and minimizing parasitic capacitance, thereby controlling the integration and reset periods independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate reset circuit is used to reset the output voltage, then the output voltage can be reset, but the circuit complexity increases and parasitic capacitance increases
Solution Approach 1:
The patent merges the reset function with the existing voltage sampling circuit by adding a reset switch that connects the sampling capacitor to ground. This integration eliminates the need for a separate reset circuit, reducing circuit complexity while maintaining the output voltage reset capability. The reset switch is controlled by a reset signal that is generated within the same circuit system.
2Reliability
If a separate reset circuit is used to reset the output voltage, then the output voltage can be reset, but parasitic capacitance increases
Solution Approach 1:
The patent combines the reset function with the voltage sampling capacitor, using the same capacitor for both sampling and reset operations. This eliminates the need for additional capacitors that would increase parasitic capacitance. The reset switch provides a low-impedance path to ground when activated, effectively resetting the voltage without introducing significant parasitic capacitance.
3Reliability
If the output voltage is reset using a separate reset circuit, then the reset function is achieved, but the operating speed decreases due to RC time constant
Solution Approach 1:
The patent integrates the reset function with the voltage sampling circuit, allowing the same capacitor to be used for both sampling and resetting operations. This eliminates the need for a separate RC time constant associated with a dedicated reset circuit. The reset switch provides a direct discharge path that is not limited by additional RC time constants, thereby maintaining high operating speed.
4Area of stationary object
If the circuit size is reduced, then the integration density increases, but the voltage sampling and reset functions may be compromised
Solution Approach 1:
The patent merges the voltage sampling and reset functions into a single integrated circuit block. The voltage sampling capacitor serves dual purposes: storing the sampled voltage and being reset by the reset switch. This consolidation reduces the overall circuit area while maintaining both sampling and reset functionalities, as the same hardware components perform multiple functions.
Solution Approach 2:
The voltage sampling capacitor is designed to serve multiple functions: it stores the sampled voltage during the sampling phase and is subsequently reset during the reset phase. The reset switch, when activated, provides a discharge path for the capacitor. This multi-functionality approach allows the circuit to maintain both sampling and reset capabilities within a compact area, improving integration density without compromising functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster operation with a smaller size, solving the time constant problem of the RC circuit and reducing parasitic capacitance, resulting in improved speed and reduced noise sensitivity.
Implementation Method 1
an output voltage output by integrating the input voltage for a predetermined set time (T)
Implementation Method 2
resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated
Implementation Method 3
The voltage sampling circuit may include a first switch, a second switch, a first capacitor, and a second capacitor
Data Source
AI summary
According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).