Current Mode Multiply-Accumulate Core for Low Power ML
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Solution Overview
Problem
Current machine learning engines for AI applications face challenges with ultra-low power consumption, high throughput, and real-time processing due to inherent nonlinearity and area inefficiencies in switched capacitor structures, and lack of digital equivalent outputs from classical analog circuits.
Innovation Solution
The development of current mode hardware cores for machine learning applications, featuring parallel current paths, current mode interfaces, and comparators, which enable low power, high throughput, and real-time processing by using current mode multiply-accumulate cores and bidirectional current mode computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If switched capacitor structures are used for digital ML engines, then digital equivalent output is achieved, but area consumption increases and nonlinearity issues occur
Solution Approach 1:
The patent replaces traditional switched capacitor structures with current mode circuitry. Current mode circuits perform multiply-accumulate operations using current mirrors and transconductance amplifiers, eliminating the need for large switched capacitor arrays while maintaining digital output precision through subsequent quantization circuits.
Solution Approach 2:
The patent changes the fundamental operating parameter from voltage-based switched capacitors to current-based operations. By using transconductance amplifiers to convert voltages to currents and performing computations in the current domain, the system achieves both compact area and precise digital outputs through controlled current mirrors and quantization.
2Use of energy by stationary object
If classical analog circuits are used for low power signal processing, then power consumption decreases, but digital equivalent output is not provided
Solution Approach 1:
The patent introduces quantization circuits as an intermediary between the analog current mode computation core and the digital output interface. These quantization circuits convert the continuous current outputs into discrete digital values, bridging the gap between low-power analog processing and digital equivalent outputs required for ML applications.
Solution Approach 2:
The patent replaces purely analog output stages with a hybrid architecture that includes current mode computation followed by quantization and digital output. This substitution maintains the low power benefits of analog current mode operation while providing the digital equivalent outputs necessary for ML engine functionality.
3Measurement precision
If digital blocks are used for ML processing, then digital equivalent output is achieved, but power consumption increases
Solution Approach 1:
The patent segments the ML engine into distinct functional blocks: current mode multiply-accumulate units for computation, quantization circuits for conversion, and decision-making blocks for output. This segmentation allows each block to operate in its optimal domain (analog current mode for computation, digital for output), minimizing overall power consumption while maintaining digital equivalent outputs.
Solution Approach 2:
The patent employs periodic switching and clocking schemes in the current mode circuitry to perform computations only when needed, rather than continuous operation. This periodic action reduces average power consumption while still achieving the required digital output precision through synchronized quantization and output stages.
Data Source
AI summary
An apparatus includes a current-mode multiply-accumulate (MAC) core with a plurality of parallel current carrying paths. Each path is configured to carry a unit current based on a state of an input variable, a weight, and a configuration vector. The plurality of current carrying paths are arranged in groups, and each group has a summation line. Also included are a plurality of current mode interfaces. Each current mode interface of the plurality of current mode interfaces is coupled to a corresponding summation line of the plurality of summation lines. A plurality of current mode comparators are coupled to the plurality of current mode interfaces and configured to compare current on the corresponding one of the plurality of summation lines to a plurality of corresponding reference currents.