Current-Mode Memory Circuit for Fast Low-Voltage Data Transfer
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Solution Overview
Problem
Semiconductor memory devices face issues with data transfer speed and power consumption due to circuit inefficiencies when operating at different supply voltages or experiencing fabrication process variations, leading to degraded signal levels.
Innovation Solution
The memory device incorporates a select circuit and circuit stages with driver, current sensing, and precharge/equilibrate circuits, where transistors are controlled by different signals to manage voltage differences between input and output signals, optimizing data transfer by reducing the number of circuit stages needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a circuit operates at a lower supply voltage, then power consumption is reduced, but data transfer speed and signal level values degrade
Solution Approach 1:
The patent employs multiple circuit stages with progressively increasing voltage levels to transfer data signals. Each stage boosts the signal voltage, allowing the overall system to achieve high-speed data transfer while individual stages can operate at lower voltages, thus reducing power consumption at each stage.
Solution Approach 2:
The data transfer circuit is divided into multiple discrete circuit stages. Each stage performs a portion of the voltage boosting function, allowing the system to achieve high output voltages through sequential stages rather than requiring a single high-voltage stage, which reduces power consumption while maintaining data transfer speed.
2Manufacturing precision
If fabrication process variations occur, then signal level values are degraded, but device complexity increases to compensate
Solution Approach 1:
The patent uses multiple circuit stages that progressively adjust voltage levels to compensate for fabrication process variations. Each stage can be optimized to provide the necessary voltage boost, ensuring consistent signal level values across different manufacturing batches without requiring excessive complexity in individual stages.
Solution Approach 2:
The multi-stage circuit architecture provides inherent feedback mechanisms where each stage's output feeds into the next stage's input. This allows automatic compensation for process variations, as each stage adjusts the signal level based on the actual input it receives, maintaining consistent output signal levels despite manufacturing tolerances.
3Productivity
If more circuit stages are used to maintain signal levels, then data transfer speed increases, but device size increases
Solution Approach 1:
The patent combines multiple functions within each circuit stage, including voltage boosting, signal conditioning, and level shifting. By merging these functions into integrated stages rather than using separate circuits for each function, the patent achieves high data transfer speeds with a compact device footprint.
Solution Approach 2:
Each circuit stage is designed to perform multiple functions: voltage amplification, signal level adjustment, and preparation for the next stage. This multi-functionality reduces the total number of discrete components needed, thereby reducing device size while maintaining the data transfer speed benefits of multiple stages.
Data Source
AI summary
Some embodiments include a first circuit to drive signals at first circuit output nodes, and a second circuit to generate output signals at second circuit output nodes. The second circuit includes a first transistor coupled between a supply node and a first node of the second circuit output nodes and a second transistor coupled between the supply node and a second node of the second circuit output nodes. Each of the first and second transistors includes a gate coupled to one of the first and second nodes. Other embodiments including additional apparatus, systems, and methods are disclosed.