Current-Mode Pipelined ADC for High-SNR Low-Power Conversion
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face challenges in achieving high signal-to-noise ratio (SNR) and conversion bandwidth in low voltage deep submicron processes, with pipelined ADCs being power hungry and SAR ADCs not readily scalable for deep sub-micron technologies while maintaining power efficiency.
Innovation Solution
A multi-stage pipelined ADC system is introduced, utilizing a current steering first stage and a cascaded SAR second stage, employing a low power current steering DAC approach that replaces switched capacitor networks with feedback resistors for residue current signal conversion, enabling high sampling rates and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pipelined ADC architecture is used, then conversion bandwidth and signal-to-noise ratio are improved, but power consumption increases
Solution Approach 1:
The ADC is divided into multiple stages: a first sub-ADC stage for coarse conversion and a second sub-ADC stage for fine conversion. This segmentation allows each stage to operate more efficiently, reducing overall power consumption while maintaining high signal-to-noise ratio through progressive refinement of the digital representation.
Solution Approach 2:
The patent transitions from traditional voltage-mode operation to current-mode operation in the first sub-ADC stage. This dimensional change in the signal domain enables faster conversion and reduced power consumption by exploiting the inherent speed and efficiency of current-mode circuits in deep submicron processes.
2Use of energy by moving object
If SAR ADC architecture is used, then power efficiency is improved, but scalability to deep sub-micron processes deteriorates
Solution Approach 1:
The patent employs dynamic current steering in the first sub-ADC stage, where current sources are dynamically controlled based on the digital code from the flash converter. This dynamic operation enables the circuit to adapt to deep submicron process characteristics, maintaining scalability while preserving power efficiency through intelligent resource allocation.
3Productivity
If current steering DAC approach is used, then sampling rate is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the current steering DAC functionality with the first sub-ADC stage by using the same current sources for both digital-to-analog conversion and residue generation. This integration reduces overall circuit complexity while maintaining high sampling rates, as the current steering mechanism serves dual purposes in the pipeline architecture.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.