Current-Mode PLL Loop Filter for Jitter Reduction
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving high bandwidth and low jitter performance while being sensitive to process, power supply, and temperature variations, which complicates design and stability.
Innovation Solution
A self-biased PLL with a current-mode loop filter and charge pump circuit, featuring a current-controlled oscillator and a feedback divider with a programmable prescaler, is designed to maintain stability and performance across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional voltage-mode PLL circuits are used, then the design is straightforward with well-established components, but the circuit exhibits sensitivity to process, power supply, and temperature variations, resulting in limited bandwidth and higher jitter
Solution Approach 1:
The patent replaces the traditional voltage-mode loop filter with a current-mode loop filter, substituting voltage-based operation with current-based operation. This substitution enables the PLL to achieve better immunity to process, power supply, and temperature variations while maintaining design feasibility through systematic current-mode design techniques
Solution Approach 2:
The patent changes the fundamental operating parameter of the loop filter from voltage to current. By using current-mode operation with self-biasing circuits, the PLL achieves improved stability margins and reduced sensitivity to environmental variations, while the self-biasing mechanism automatically adjusts operating points to maintain performance across different conditions
2Reliability
If the PLL bandwidth is increased to reduce jitter, then the jitter performance improves, but the circuit becomes more sensitive to process and temperature variations
Solution Approach 1:
The patent implements self-biasing feedback mechanisms in the current-mode loop filter that automatically adjust the operating point based on process and temperature conditions. This feedback ensures that the PLL maintains optimal bandwidth and jitter performance while compensating for environmental variations, allowing high bandwidth operation without increased sensitivity
Solution Approach 2:
The current-mode loop filter incorporates self-biasing circuits that automatically regulate their own operating points without external control. This self-service capability enables the circuit to maintain stable performance across process and temperature variations while achieving the desired bandwidth and jitter characteristics
3Ease of manufacture
If a general-purpose PLL design is created to accommodate multiple output frequencies, then design resources are reduced, but the circuit complexity increases
Solution Approach 1:
The patent designs a general-purpose current-mode PLL that can generate multiple output frequencies through a unified architecture. The current-mode loop filter and self-biasing circuits provide a flexible platform that can be configured for different frequency requirements without requiring separate dedicated circuits, achieving multi-functionality with moderate complexity increase
Data Source
AI summary
A phase-locked loop (PLL) includes a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom and a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal. The PLL further includes a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current. The current-mode loop filter circuit may be self-biased. For example, the current-mode loop filter circuit and the charge pump may be biased responsive to a common bias control signal generated by the current-mode loop filter circuit.