Current-Mode Logic Latch for Balanced Quadrature Signals
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Solution Overview
Problem
In digital communication systems, maintaining the 90° phase relationship between I and Q signals while avoiding the use of a dummy load, which can affect amplitude, waste power, and generate heat.
Innovation Solution
A current mode logic latch circuit is used, where the input-tracking and data storage stages are activated by the combined I and Q signals, reducing power consumption by requiring less bias current and eliminating the need for a dummy load, thus ensuring equal loading and phase retention of the signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy load is connected to the Q signal to maintain the 90° phase relationship, then the quadrature relationship is preserved, but power is wasted and additional heat is generated
Solution Approach 1:
The patent removes the dummy load component from the system entirely. Instead of connecting a dummy load to the Q signal to maintain the 90° phase relationship, the invention uses a current mode logic latch circuit that inherently balances the loading on both I and Q signals through its differential circuit architecture, eliminating the need for the dummy load and thus eliminating the associated power waste and heat generation.
Solution Approach 2:
The patent changes the operating parameters of the circuit by using current mode logic instead of voltage mode logic. This parameter change enables the latch circuit to present equal loading conditions to both I and Q signals through its differential current switching mechanism, thereby maintaining the quadrature relationship without requiring a dummy load and reducing overall power consumption.
2Reliability
If a dummy load is connected to the Q signal to maintain the 90° phase relationship, then the quadrature relationship is preserved, but the relative amplitude of the Q signal is affected
Solution Approach 1:
The patent removes the dummy load component that was causing amplitude degradation of the Q signal. The current mode logic latch circuit provides symmetric loading to both I and Q signals through its differential architecture, eliminating the amplitude distortion that occurred when a dummy load was connected to the Q signal while maintaining the 90° phase relationship.
3Reliability
If a dummy load is connected to the Q signal to maintain the 90° phase relationship, then the quadrature relationship is preserved, but additional heat is generated
Solution Approach 1:
The patent removes the dummy load component that was generating unnecessary heat. By using a current mode logic latch circuit with differential switching, the invention achieves balanced loading on both I and Q signals without the dummy load, thereby eliminating the heat generation associated with the dummy load while maintaining the quadrature relationship.
4Device complexity
If asymmetric loading is applied to I and Q signals in a down-converter, then circuit complexity is reduced, but the phase relationship between I and Q signals deteriorates
Solution Approach 1:
The patent merges the functions of the I and Q signal paths by using a current mode logic latch circuit with differential switching that treats both signals symmetrically. The differential pair structure and cross-coupled feedback mechanism ensure that both I and Q signals experience identical loading conditions, maintaining the 90° phase relationship while keeping the circuit configuration relatively simple through the use of standard current mode logic building blocks.
Data Source
AI summary
Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals.