Current-Mode Sense Amplifier with Cross-Coupled Inverters
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Solution Overview
Problem
Current sense amplifiers face challenges in reducing power consumption and increasing clock frequency due to high capacitance in bit lines, leading to inefficiencies in reading data from memory cells, particularly in digital circuitry where cross-talk between nodes is a concern.
Innovation Solution
A current sense amplifier design incorporating a pair of cross-coupled inverters, a transmission gate, and a reference current source, which enables current limitation in both 'match' and 'mismatch' cases, reduces DC currents and cross-talk by decoupling input and output nodes, and allows for effective switching and resetting to prepare for sensing phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current sense amplifiers are used to read data from memory cells, then data reading capability is improved, but power consumption increases due to high capacitance in bit lines
Solution Approach 1:
The sense amplifier operates in periodic phases (precharge phase and sense phase) controlled by clock signals. During the precharge phase, bit lines are precharged to a reference voltage. During the sense phase, the actual sensing operation occurs. This periodic operation allows the amplifier to reset and prepare for each sensing operation, enabling continuous operation while controlling power consumption through phased execution rather than continuous operation.
Solution Approach 2:
The patent employs dynamic voltage scaling where the reference voltage level is adjusted based on operating conditions. The sense amplifier can operate with different reference voltages (e.g., Vref, Vref/2) depending on the data pattern and process conditions. This parameter adaptation allows the circuit to maintain sensing accuracy while optimizing power consumption for different operating scenarios.
2Productivity
If current sense amplifiers operate at higher clock frequencies, then productivity is improved, but cross-talk between nodes increases
Solution Approach 1:
The patent introduces dummy nodes and isolation structures as intermediaries between adjacent sense amplifier circuits. These dummy nodes act as buffers that prevent direct coupling between neighboring circuits. Additionally, the bit line structure incorporates isolation segments that reduce capacitive coupling between adjacent bit lines, thereby minimizing cross-talk while allowing high-frequency operation.
Solution Approach 2:
The sense amplifier circuit is divided into separate functional blocks with isolated input and output nodes. The bit lines are segmented into smaller sections with isolation elements between them. This segmentation reduces the overall coupling capacitance between adjacent circuits, enabling higher clock frequencies without excessive cross-talk interference.
3Use of energy by moving object
If DC currents are reduced to lower power consumption, then use of energy is improved, but sensing accuracy deteriorates
Solution Approach 1:
The sense amplifier maintains continuous readiness for sensing operations through the precharge phase, where bit lines are continuously held at a reference voltage level. This continuous preparation ensures that when a sensing operation is initiated, the amplifier is already in the optimal state for accurate current comparison, eliminating the need for high continuous DC bias currents while maintaining sensing accuracy.
Solution Approach 2:
The circuit employs dynamic current mirroring and adaptive biasing where the effective sensing current is dynamically adjusted during operation. The amplifier uses switched current sources that provide high current only during the brief sensing window, rather than maintaining high DC current continuously. This dynamic operation reduces average power consumption while preserving peak sensing accuracy.
Data Source
AI summary
A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.