Current-Mode Time-Interleaved ADC Circuitry for Gain Skew Matching
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Solution Overview
Problem
Existing time-interleaved analogue-to-digital converters (ADCs) face challenges in achieving high speed and linearity due to difficulties in gain and skew matching, random mismatches, and signal-dependent switching delays, which result in distortion and noise, especially at high frequencies.
Innovation Solution
The implementation of current-mode circuitry using sinusoidal control signals to steer charge packets along different paths, allowing for improved matching and calibration without the need for direct measurement of clock delays, and employing passive resistance for input impedance conversion to reduce noise and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved ADC architecture is used to increase sampling speed, then sampling rate is improved, but gain and skew matching between channels becomes difficult to achieve
Solution Approach 1:
The patent replaces voltage-mode switching mechanisms with current-mode circuitry. Current-mode operation eliminates signal-dependent delays and reduces sensitivity to timing skew, thereby maintaining high sampling rates while improving gain and skew matching between channels. The current-mode sample-and-hold circuitry and demultiplexers provide more consistent channel matching without requiring complex calibration.
Solution Approach 2:
The patent changes the operating parameters by using sinusoidal control signals instead of traditional clock signals. This parameter change allows for smoother switching transitions and reduces abrupt changes in gain and phase across channels, improving overall matching. Additionally, the use of current-mode operation changes the fundamental operating regime from voltage-based to current-based, which inherently provides better matching characteristics.
2Ease of manufacture
If traditional voltage-mode circuitry is used, then circuit design is straightforward, but signal-dependent switching delays cause distortion at high frequencies
Solution Approach 1:
The patent substitutes voltage-mode switching with current-mode switching throughout the signal path. Current-mode switches exhibit signal-independent switching behavior because they operate with fixed voltage levels, eliminating the signal-dependent delays that plague voltage-mode circuits at high frequencies. This substitution maintains design simplicity while removing the harmful distortion effects.
3Manufacturing precision
If calibration is performed to correct gain and skew mismatches, then matching accuracy is improved, but ADC must be taken offline causing loss of time
Solution Approach 1:
The patent implements preliminary matching through current-mode circuit design that inherently provides consistent gain and skew characteristics across channels. By building in matching capabilities during the design phase through current-mode operation, the need for extensive offline calibration is reduced, allowing faster calibration or even calibration-free operation.
Solution Approach 2:
The current-mode architecture provides self-matching characteristics that automatically maintain consistency across channels without requiring external calibration intervention. The circuitry self-corrects for many matching errors through its inherent operational characteristics, reducing or eliminating the need for offline calibration procedures.
4Speed
If multiple time-interleaved sub-ADCs are used to achieve high speed conversion, then sampling rate is improved, but device complexity increases
Solution Approach 1:
The patent merges the sampling and demultiplexing functions into integrated current-mode circuit blocks. By combining these functions in current-mode architecture, the number of discrete components is reduced while maintaining the time-interleaved high-speed operation. The current-mode sample-and-hold and demultiplexer stages are integrated more tightly, reducing overall device complexity.
Data Source
AI summary
There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.