Current-Mode Write Driver H-Bridge for Dead-Band-Free Switching
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Solution Overview
Problem
Conventional write drivers for hard disk drives face challenges in achieving high switching speed while maintaining low power operation, often resulting in dead bands and saturated H-bridge transistors due to their open loop configuration and voltage-to-current-to-voltage translation architecture.
Innovation Solution
The development of current mode write drivers that directly convert ECL differential voltage signals into DC and boost output currents, eliminating the need for voltage conversions and using an H-bridge circuit with current sourcing and sinking control nodes and current mirrors to deliver current diagonally through the load, thereby avoiding dead bands and saturated transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional voltage-to-current-to-voltage translation architecture is used, then the write driver can operate in open loop configuration, but dead bands and saturated H-bridge transistors occur resulting in sluggish response
Solution Approach 1:
The patent replaces the conventional voltage-to-current-to-voltage translation architecture with a direct current mode architecture. Current mode circuits directly control the H-bridge transistors without intermediate voltage conversions, eliminating dead bands and saturation effects. This substitution of the control mechanism fundamentally resolves the sluggish response issue while maintaining high switching speed.
2Productivity
If high switching speed is achieved through open loop configuration, then data density increases, but power consumption increases and dead bands occur
Solution Approach 1:
The patent changes the operational parameters from voltage mode to current mode throughout the signal path. By maintaining current mode operation from the input stage through the H-bridge to the output, the system achieves high switching speed necessary for high data density while improving power efficiency. The direct current control eliminates the power-wasting voltage conversions and reduces dead band effects that increase effective power consumption.
3Adaptability or versatility
If voltage conversions are performed multiple times (voltage to current to voltage to current), then the circuit can interface with different stages, but switching speed decreases and jitter increases
Solution Approach 1:
The patent segments the write driver into distinct current mode stages: a current mode input stage, a current mode H-bridge driver stage, and a current mode output stage. Each stage operates natively in current mode, eliminating the need for repeated voltage-to-current and current-to-voltage conversions. This segmentation maintains circuit adaptability while dramatically improving switching speed and reducing jitter by removing conversion bottlenecks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high switching speed with low power operation, reducing jitter and power dissipation, and allows for higher data density storage by eliminating dead bands and saturated transistors, while maintaining high linearity.
Implementation Method 1
The write head is essentially a small coil of wire which stores data by magnetizing small regions along a disk's tracks. During a write operation a current driven through the write head in a first direction magnetizes a small region of the disk under the head at a first orientation
Data Source
AI summary
An integrated circuit (100) includes a current mode write driver (105). The write driver (105) includes a switching control circuit (110) including (i) a DC current control circuit (111) operable to directly convert a received ECL differential signal into first, second, third and fourth DC output currents (a, b, c, and d) and (ii) a boost current control circuit (112) operable to directly convert a received level shifted version of the ECL differential voltage signal and a delayed version of the ECL differential voltage signal into first, second, third and fourth boost output currents (a1, b1, c1, and d1). An H-bridge circuit (120) includes an output stage (125) including first and second current sourcing control nodes (126, 127) and first and second current sinking control nodes (128, 129). A first output node (131) is between the first sourcing and first sinking nodes (126, 128) and second output node between the second sourcing and the second sinking nodes (127, 129). A first, second, third and fourth current mirror including input is coupled to sourcing or sinking control nodes (126, 127, 128, and 129) and are each operable to receive one of the DC output currents and one of the boost output currents for switchably delivering current diagonally through a load (145) connected between the output nodes (131, 132).