Current Page Translation Register for Low Latency Memory Access
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Solution Overview
Problem
In processor systems supporting virtual memory, the translation of virtual addresses to physical addresses and permission data retrieval can result in significant latency and increased dynamic power consumption due to the reliance on micro-translation look-aside buffers (μTLBs) and Memory Management Units (MMUs, especially when μTLB entries are invalidated or miss latency occurs.
Innovation Solution
Implementing a current page translation register that caches virtual to physical address translation data and optional access permission data, providing an additional caching level above typical translation look-aside buffers, which reduces page hit/miss determination time and power consumption by storing frequently accessed page data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual address translation is performed through μTLB/MMU for every access, then address translation accuracy is ensured, but translation latency increases significantly (tens to hundreds of cycles)
Solution Approach 1:
The patent pre-fetches and stores translation data for the current page in the translation data storage unit before actual memory access occurs. When a virtual address falls within the current page range, the pre-stored translation data is directly used, avoiding real-time μTLB/MMU lookup and reducing translation latency from tens/hundreds of cycles to essentially one cycle.
Solution Approach 2:
Instead of maintaining full page table translation capabilities in the fast path, the patent implements a partial solution by caching only the current page's translation data in the translation data storage unit. This partial caching approach provides sufficient accuracy for within-page accesses while dramatically reducing the complexity and latency compared to full μTLB/MMU operation.
2Speed
If μTLB is implemented in SRAM memory to provide fast translation, then translation speed is improved, but dynamic power consumption increases
Solution Approach 1:
The patent extracts the translation data storage function from the traditional μTLB SRAM structure and implements it as a separate translation data storage unit. This extracted storage unit is optimized for power efficiency by storing only the current page's translation data rather than maintaining a large associative cache, thereby achieving fast translation speeds with significantly reduced dynamic power consumption compared to conventional SRAM-based μTLB.
3Reliability
If μTLB entries are invalidated by MMU to maintain translation accuracy, then address translation reliability is improved, but μTLB miss latency increases and power consumption increases
Solution Approach 1:
The system pre-fetches translation data from the MMU and stores it in the translation data storage unit before it is needed for actual memory accesses. This preliminary action ensures that when the MMU invalidates μTLB entries, the translation data is already available in the storage unit, eliminating μTLB miss latency and avoiding the need for power-consuming re-fetch operations.
Solution Approach 2:
The translation data storage unit acts as an intermediary between the MMU and the address translation process. It buffers translation data independently of μTLB validity states, allowing the system to maintain translation accuracy through MMU validation while avoiding the performance penalty of μTLB misses. The intermediary storage decouples the reliability function (MMU validation) from the speed function (translation execution).
Data Source
AI summary
This invention provides a current page translation register storing virtual to physical address translation data for a single current page and optionally access permission data for the same page for program accesses. If an accessed address is within the current page, the address translation and permission data is accessed from current page translation register. This current page translation register provides an additional level of caching of this data above the typical translation look-aside buffer and micro translation look-aside buffer. The smaller size of the current page translation register provides faster page hit/miss determination and faster data access using less power than the typical architecture. This is helpful for program access which generally hits the current page more frequently than data access.