Current-Controlled Phase Interpolation Circuit for Linear Clock Division
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Solution Overview
Problem
Existing phase interpolation circuits suffer from deteriorated linearity due to variations in transistor threshold voltages across multiple stages, which affect the accuracy of phase division.
Innovation Solution
A phase interpolation circuit with a current source circuit, discharging transistor, and current control circuit that sets the current ratio between two clock signals to generate an interpolation clock signal, using a current source circuit between power supply nodes and a discharging transistor to manage current flow based on phase interpolation signals, and an output circuit to produce the interpolated signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple stages of phase-dividing units are coupled to divide the phase by 2^n, then the phase division capability is improved, but the linearity of the phase is deteriorated due to transistor threshold voltage variation
Solution Approach 1:
The patent changes the control parameter from voltage-based phase division to current-based phase division. By controlling the current ratio between first and second current sources using a phase interpolation signal, the circuit achieves accurate phase interpolation without suffering from transistor threshold voltage variations that plague voltage-based multi-stage phase dividers. The current ratio directly determines the phase difference, providing linear and accurate phase control.
Solution Approach 2:
The patent introduces a current control circuit as an intermediary between the phase interpolation signal and the phase-dividing units. This intermediary converts the phase interpolation signal into appropriate current ratios for the first and second current sources, thereby indirectly controlling the phase division process and eliminating the direct impact of transistor threshold voltage variations on phase linearity.
2Ease of manufacture
If transistor threshold voltage variations are present in coupled phase-dividing units, then manufacturing simplicity is maintained, but phase division accuracy is deteriorated
Solution Approach 1:
The patent changes the controlling parameter from voltage to current. By using current sources whose ratios are controlled by the phase interpolation signal, the circuit becomes insensitive to transistor threshold voltage variations. The current ratio directly determines phase difference, providing accurate phase division without requiring precise matching of transistor threshold voltages, thus maintaining ease of manufacture while improving phase division accuracy.
3Measurement precision
If current ratio between first current and second current is adjusted based on phase interpolation signal, then phase interpolation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase interpolation function into distinct current sources (first and second current sources) that can be independently controlled. Each current source responds to the phase interpolation signal by providing a proportional current, and their combined effect at the first node produces the desired phase interpolation. This segmentation simplifies the control mechanism while maintaining high accuracy.
Solution Approach 2:
The current control circuit serves as an intermediary that translates the phase interpolation signal into appropriate current ratios. This intermediary layer simplifies the overall control architecture by providing a direct current-based control mechanism, avoiding the need for complex multi-stage voltage-based phase division circuits while achieving high phase interpolation accuracy.
Data Source
AI summary
A phase interpolation circuit configured to generate an interpolation clock signal obtained by performing phase interpolation between clock signals includes a current source circuit that is disposed between a power supply node and a node and supplies the node with a current that flows when one of the clock signals is active and a current that flows when the other of the clock signals is active, a discharging transistor that is disposed between the node and the power supply node and is turned on when the clock signals are inactive, a current control circuit configured to set a current ratio between the currents based on a phase interpolation signal that instructs a ratio of phase interpolation between the clock signals, and an output circuit configured to output an interpolation clock signal based on a signal at the node.