Complementary Current-Reuse Frequency Doubler for Low-Power mmWave LO
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Solution Overview
Problem
Existing millimeter-wave (mmW) receivers face challenges with high power consumption, poor noise performance, and suboptimal integration due to subharmonic LO distribution and bias points optimized for maximum RF performance, which increase power consumption and real estate.
Innovation Solution
Employing an even harmonic multiplier with complementary current reuse and supply voltage and current density scaling, utilizing transformer circuits and complementary transistors to minimize power consumption and enhance areal efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bias points are optimized for maximum RF performance with high drain voltages and current densities, then RF performance (NFmin, Fmax) is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating parameters by using complementary current reuse to cancel even-order distortion products, enabling operation at lower current densities while maintaining RF performance. This parameter change allows the circuit to operate away from the traditional high-power bias points, achieving both good RF performance and lower power consumption
2Device complexity
If subharmonic LO distribution is used to simplify LO distribution in phased array systems, then device complexity is reduced, but frequency multipliers are required which increase power consumption
Solution Approach 1:
The patent extracts and eliminates the need for traditional frequency multipliers by using complementary current reuse in a push-push configuration. The even-order distortion products that would normally require filtering are instead reused as useful signals, taking out the need for separate frequency multiplication stages and their associated power consumption
3Speed
If traditional frequency multipliers are used to achieve required LO frequency, then frequency multiplication is achieved, but occupied area and power consumption increase
Solution Approach 1:
The patent merges the frequency multiplication function with the amplifier function into a single complementary push-push stage. By combining these functions, the circuit achieves frequency multiplication without requiring separate multiplier components, thereby reducing occupied area while maintaining the required LO frequency
Data Source
AI summary
An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and/or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.