Current Sense Amplifier Readout for Low-Voltage SRAM Stability
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Solution Overview
Problem
SRAM cells experience device variation-induced mismatches and stability issues at low supply voltages, leading to read current reduction and data corruption, while high supply voltages cause stability loss, necessitating improved sense amplifiers for stable read operations.
Innovation Solution
A current sense amplifier is used that operates concurrently with word line assertion, allowing faster access times and reducing power consumption by temporarily isolating supply voltage from the latch circuit during read operations, especially in low voltage modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage sense amplifiers are used in SRAM, then read operation can be performed, but wait time is required for bit line voltage differential to develop
Solution Approach 1:
The patent replaces voltage-based sensing with current-based sensing. The current sense amplifier detects current differences directly from the bit lines during the read operation, eliminating the need to wait for voltage differentials to develop. This substitution of the sensing mechanism fundamentally changes the operation from voltage measurement to current measurement, achieving faster access without compromising reliability.
2Use of energy by stationary object
If lower supply voltage VDD is provided, then power consumption is reduced, but device variation induced mismatches increase and read stability decreases
Solution Approach 1:
The patent changes the sensing parameter from voltage to current. By using current mode sensing instead of voltage mode sensing, the system can operate reliably at lower supply voltages where voltage differentials are difficult to establish. The current sense amplifier directly detects the current difference between bit lines, which remains sufficient even at low VDD, thereby maintaining read stability while enabling lower power operation.
3Loss of time
If word line duration is extended, then more time is available for read operation, but data stored in SRAM cell becomes corrupted
Solution Approach 1:
The patent replaces voltage-based sensing with current-based sensing, which provides faster detection of data on the bit lines. This substitution enables the read operation to complete in a shorter time window, preventing data corruption that would occur with extended word line assertion. The current mode sensing achieves faster access times that are sufficient to read data before it becomes corrupted.
4Reliability
If conventional sense amplifiers are used, then read operation is supported, but tracking circuits are required which increase device complexity
Solution Approach 1:
The patent extracts and removes the tracking circuits from the sense amplifier design. By using current mode sensing with a simplified latch-based differential amplifier, the system achieves reliable read operation without requiring the complex tracking circuits that are necessary in voltage mode sense amplifiers. This extraction of unnecessary components reduces device complexity while maintaining read functionality.
Data Source
AI summary
A memory device includes a memory array and a sense amplifier. The sense amplifier operates with a first supply voltage and be enabled, in response to an enable signal, to receive first and second current signals from the memory array through first and second nodes, and includes a pull-up circuit and a latch circuit. The pull-up circuit is coupled between a first supply voltage terminal and the first to second nodes, and couples, in response to a first control signal having a low logic state, the first supply voltage terminal to the first and second nodes. The latch circuit generates, in response to the first and second current signals received from the first and second nodes, first and second output signals for determining a data stored in a memory cell in the memory array when the first supply voltage terminal is coupled to the first and second nodes.


