Current Starved Delay Lines for DC-DC Converter PWM Control
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Solution Overview
Problem
Conventional DC-DC converters face challenges in achieving high switching frequency and very narrow duty ratio operations due to limitations in component speed and power consumption, particularly with high-speed comparators, artificial voltage ramp generators, and high-frequency oscillators, which are costly and power-hungry, and struggle with accurate minimum ON time generation at high switching frequencies.
Innovation Solution
The solution involves using current starved delay lines and simple logic circuits, such as RS flip-flops, to generate constant frequency PWM control signals without relying on high-speed comparators, artificial voltage ramp generators, and high-frequency oscillators, allowing for accurate control of power switches and minimizing ON time, thereby enabling efficient PWM and PFM control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional high-speed comparators and artificial voltage ramp generators are used for PWM control, then high switching frequency operation is achieved, but power consumption increases and cost increases
Solution Approach 1:
The patent extracts and removes the power-hungry artificial voltage ramp generator from the PWM control architecture. Instead, it uses a simple clock signal combined with delay lines to generate the necessary timing signals, eliminating the need for the complex and power-consuming ramp generator while maintaining high switching frequency operation.
Solution Approach 2:
The patent replaces expensive, power-hungry high-speed comparators and artificial voltage ramp generators with simpler, lower-cost delay line circuits and logic gates. These simpler components consume significantly less power while achieving the same high switching frequency PWM control function.
2Speed
If conventional high-speed comparators are used for narrow duty ratio control, then high switching frequency is achieved, but propagation delay increases and duty ratio control precision deteriorates
Solution Approach 1:
The patent replaces the mechanical/electronic comparison process in conventional comparators with a time-based delay line system. By using precise delay lines and clock signals, the duty ratio is controlled through time delays rather than voltage comparisons, eliminating propagation delay issues and achieving superior duty ratio control precision at high switching frequencies.
3Speed
If artificial voltage ramp generators are used for PWM control, then high switching frequency operation is enabled, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the artificial voltage ramp generator from the control circuit, replacing it with a simple clock signal source and delay lines. This dramatically reduces device complexity while maintaining the ability to operate at high switching frequencies with precise duty ratio control.
4Power
If high switching frequency operation is implemented, then power density increases, but switching losses increase at light load conditions
Solution Approach 1:
The patent implements dynamic switching frequency adjustment through Pulse Frequency Modulation (PFM) mode. At light load conditions, the switching frequency is automatically reduced to minimize switching losses. The control circuit can dynamically switch between PWM mode (for high power density requirements) and PFM mode (for light load efficiency), optimizing performance across all operating conditions.
5Speed
If conventional PWM comparators are used for very narrow duty ratio control, then high switching frequency is achieved, but propagation delay limits the minimum duty ratio
Solution Approach 1:
The patent replaces the voltage comparison mechanism with a time-based delay line mechanism. By using precise delay lines synchronized to the clock signal, the system can generate very narrow duty ratios without being limited by comparator propagation delay. The duty ratio is determined by the delay line settings rather than by voltage threshold crossing, eliminating the propagation delay bottleneck.
Data Source
AI summary
DC-DC power converter control comprises current starved delay lines for phase shifting control signals that set and reset a RS flip-flop to provide controllable PWM pulse widths from narrow to wide at a clock frequency. Precise pulse width control and a guaranteed minimum pulse width for pulse frequency modulation (PFM) control the DC-DC power converter during low power demand is also provided. PFM control maintains the same pulse width while decreasing the number of pulses per second when the output voltage exceeds an upper value and increases the number of pulses per second when the output voltage is less than a lower value. Voltage-to-current converters provide control currents to the current starved delay lines that provide the control signals to the SET and RESET inputs of the RS flip-flop. A D-flip-flop may further be used to improved circuit operation when generating high duty cycle (>50 percent) pulse widths.