Current-Starved TLD Circuits for Voltage Droop Clock Stretching
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Solution Overview
Problem
Adaptive clock distribution systems face challenges in effectively compensating for supply voltage droops across large integrated circuits, where voltage droops are decoupled and diminished in magnitude before reaching remote regions, leading to insufficient clock signal stretching and potential errors in clocked circuits.
Innovation Solution
Implementing a current-starved tunable-length delay (TLD) circuit that starves clock delay circuits of current in response to voltage droops, further increasing the clock signal delay to compensate for the difference in voltage droop magnitudes across the IC, and staggering compression of the clock period to avoid errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage operating margin is designed into the power supply to compensate for voltage droops, then circuit operation reliability is improved, but power consumption significantly increases
Solution Approach 1:
The TLD circuit performs preliminary action by stretching the clock period in advance before the actual voltage droop occurs. The circuit detects voltage droop conditions and proactively extends the clock period, ensuring that logic circuits have sufficient time to complete operations even when voltage droops occur, thereby maintaining reliability without needing to permanently increase power supply voltage margin
Solution Approach 2:
The system dynamically adjusts the clock period based on real-time voltage droop detection. The TLD circuit modifies the clock signal timing adaptively - stretching the period when droop is detected and maintaining normal timing when no droop occurs. This dynamic adjustment allows the system to maintain reliability only when needed, avoiding continuous power consumption increase
2Reliability
If the CPU operating frequency is reduced to provide timing margin against voltage droops, then circuit operation reliability is improved, but productivity decreases
Solution Approach 1:
The TLD circuit stretches the clock period in advance of actual voltage droop events by detecting droop conditions and proactively extending timing margins. This preliminary action ensures that logic circuits have sufficient time to complete operations before voltage droops occur, maintaining reliability without permanently reducing CPU operating frequency
Solution Approach 2:
The system dynamically adjusts clock period timing based on real-time voltage droop detection rather than using a fixed reduced frequency. The TLD circuit modifies timing adaptively - extending periods when droop is detected and maintaining normal high-frequency operation when no droop occurs, thus preserving productivity while ensuring reliability when needed
3Reliability
If a TLD circuit is used to stretch the clock signal in response to voltage droops, then timing margin is improved, but the TLD circuit experiences less voltage droop than clocked circuits in remote regions, resulting in insufficient stretching
Solution Approach 1:
The patent introduces an intermediary power supply voltage sensing circuit that indirectly measures the voltage droop experienced by remote clocked circuits. Instead of directly measuring the droop at the TLD circuit location (which would be inaccurate), the sensing circuit detects the actual droop magnitude at remote regions through the power distribution network, providing accurate feedback for proper clock period stretching
Solution Approach 2:
The system implements feedback by using the detected voltage droop magnitude from remote regions to control the TLD circuit's clock period stretching. The droop detection circuit monitors power supply voltage variations and feeds this information back to the TLD circuit, which adjusts the clock period extension proportionally to the detected droop magnitude, ensuring accurate compensation despite spatial separation
Data Source
AI summary
Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.