Current-Steering Pipelined ADC for High-Bandwidth Low-Power Conversion
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face challenges in achieving high signal-to-noise ratio (SNR) and conversion bandwidth while maintaining low power consumption, especially in deep sub-micron process technologies.
Innovation Solution
A multi-stage pipelined ADC system is proposed, featuring a current steering first stage and a cascaded successive approximation register (SAR) second stage. This approach employs both current domain and voltage domain signal processing, utilizing a low power current steering DAC method with a combined current steering DAC and transconductance amplifier cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional switched capacitor MDAC methods are used, then conversion bandwidth is achieved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-domain switched capacitor operation to current-domain continuous operation. The current steering DAC uses current sources that are continuously active rather than being switched, and the transconductance amplifier converts currents to voltages continuously, enabling high conversion bandwidth with lower power consumption by eliminating the need for high-speed switching and large capacitors.
Solution Approach 2:
The patent substitutes the mechanical switching mechanism of conventional switched capacitor DACs with a current steering mechanism. Instead of using switches to connect capacitors to different nodes, the invention uses current sources controlled by digital signals to directly steer current to the output, eliminating switching losses and reducing power consumption while maintaining high bandwidth.
2Speed
If high sampling rates are achieved, then conversion bandwidth improves, but power consumption increases
Solution Approach 1:
The patent changes the timing parameter from discrete switching events to continuous current flow. The current steering DAC maintains constant current sources that operate continuously at the sampling rate without requiring high-speed switching transitions, thereby achieving high sampling rates with reduced dynamic power consumption compared to switched capacitor approaches.
Solution Approach 2:
The patent employs periodic clocking signals to control the current steering DAC and transconductance amplifier, where the current sources are modulated at the sampling frequency. This periodic action enables high sampling rates while maintaining lower average power consumption compared to continuous switching operations in conventional architectures.
3Power
If gain-bandwidth requirements are reduced, then power consumption decreases, but amplifier design becomes more challenging
Solution Approach 1:
The patent substitutes the high-gain voltage amplifier with a transconductance amplifier that operates in the current domain. This substitution reduces the gain-bandwidth product requirement because current-mode operation inherently provides higher impedance and reduced sensitivity to parasitic effects, simplifying the amplifier design while lowering power consumption.
Solution Approach 2:
The patent changes the operating domain from voltage to current, which fundamentally alters the amplifier requirements. The transconductance amplifier converts input currents to output voltages with lower gain-bandwidth requirements compared to voltage amplifiers, reducing power consumption while the design complexity is managed through standardized current-mode circuit techniques.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.