Current-Steering ADC Pipeline for High-SNR Low-Power Conversion
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face challenges in achieving high signal-to-noise ratio (SNR) and conversion bandwidth, particularly in low voltage deep submicron processes, with pipelined ADCs being power hungry and SAR ADCs not readily scalable for deep sub-micron technologies while maintaining power efficiency.
Innovation Solution
A multi-stage pipelined ADC system is introduced, utilizing a current steering first stage and a cascaded SAR second stage, which employs current domain and voltage domain signal processing, replacing switched capacitor networks with feedback resistors to convert residue current signals to voltage signals, thereby reducing power consumption and increasing conversion rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pipelined ADC architecture is used, then conversion bandwidth and signal-to-noise ratio are improved, but power consumption increases
Solution Approach 1:
The ADC is divided into multiple stages: a first sub-ADC stage for coarse conversion and a second sub-ADC stage for fine conversion. This segmentation allows each stage to operate more efficiently, with the current steering DAC in the first stage enabling high-speed operation with reduced power consumption compared to traditional pipelined architectures.
Solution Approach 2:
The patent changes the operating domain from voltage to current by using a current steering DAC. This parameter change enables the system to achieve high conversion bandwidth and signal-to-noise ratio while reducing power consumption, as current-mode operation allows for more efficient signal processing in deep submicron processes.
2Productivity
If traditional switched capacitor networks are used, then voltage domain signal processing is achieved, but power consumption increases and conversion rate decreases
Solution Approach 1:
The patent replaces the mechanical switched capacitor network with a current steering DAC that operates in the current domain. This substitution eliminates the need for high-speed switching operations, thereby increasing the conversion rate and reducing power consumption while maintaining voltage domain output through the transconductance amplifier.
3Adaptability or versatility
If deep submicron processes are used, then device scaling is achieved, but power efficiency deteriorates with traditional architectures
Solution Approach 1:
The patent changes the signal processing domain to current mode, which is better suited for deep submicron processes. The current steering DAC and transconductance amplifier enable the system to maintain power efficiency while scaling to deep submicron technologies, as current-mode circuits exhibit better scaling characteristics than voltage-mode switched capacitor circuits.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.