Current Steering Circuit With Active Bootstrap for Fast DAC Switching
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Solution Overview
Problem
Conventional digital-to-analogue converters (DACs) for laser diode drivers face challenges in achieving high dynamic performance, such as sharp rise/fall times, high-speed switching, and low power consumption, while maintaining a large output full-scale range and minimizing power consumption during non-selection.
Innovation Solution
A circuit design featuring a cascoded current mirror with bias transistors, electronic switches, and active bootstrap switches, along with capacitors to compensate for stray capacitance effects, allowing for efficient switching and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional switching transistors are used to control current source terminals, then the DAC can provide current output, but the rise/fall times are slow and settling time is extended
Solution Approach 1:
The current source is segmented into multiple independent current sources, each controlled by its own switching transistor. This segmentation allows each transistor to control a smaller current, enabling faster switching and reduced settling time while maintaining the overall current output capability.
Solution Approach 2:
The patent changes the operating parameters of the switching transistors by optimizing their sizing and biasing conditions. Specifically, the transistors are designed with appropriate width-to-length ratios and bias voltages to achieve fast switching speeds while minimizing charge injection and feedthrough effects that would extend settling time.
2Productivity
If switching transistors are used to control current sources, then current can be switched, but power is dissipated when both transistors are off and glitches occur during switching
Solution Approach 1:
The patent employs periodic pre-charging and pre-discharging of the current source terminals before actual switching occurs. This periodic preparation action ensures that when switching transistors change state, minimal current redistribution is needed, reducing both power dissipation and switching glitches while maintaining high switching productivity.
Solution Approach 2:
The patent introduces intermediate buffer stages and compensation circuits that act as mediators between the switching transistors and the current sources. These intermediaries absorb switching transients and prevent direct coupling of glitches to the output, while also managing power dissipation through controlled charge transfer.
3Speed
If the DAC is designed for high dynamic performance, then rise/fall times improve, but the output full-scale range is reduced
Solution Approach 1:
The patent merges multiple current sources with different current levels into a single unified output. By combining fast-switching small-current sources with slower large-current sources, the system achieves both high-speed response and large output full-scale range, resolving the contradiction between speed and quantity.
Solution Approach 2:
The patent implements dynamic current source configuration where the active current sources are selectively enabled or disabled based on the required output current level. For small current changes, only fast-switching sources are activated, while for large current ranges, additional sources are engaged, thereby maintaining both speed and full-scale range dynamically.
Data Source
Figure 1
Figure 2~3
AI summary
A circuit (10) for use e.g. in digital-to-analog converters, comprises a first transistor (M1) and a second transistor (M3) having respective control terminals coupled to a first bias voltage node (VB1) and a second bias voltage node (VB2) as well as a first electronic switch (M2). The current paths through the first (M1) and second (M3) transistor and the first electronic switch (M2) are cascaded in an output current line between a circuit output node (Iout) and ground (GND). A second (M4) and a third (M5) electronic switch are provided activatable to a conductive state to provide charge transfer current paths coupling the charge transfer node (Y).