Current-Steering DAC with Alternating Sub-DAC Bias Stabilization
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Solution Overview
Problem
Conventional current-steering type digital-to-analog converters (DACs) face dynamic performance issues due to non-linear changes in internal bias points during switching transients, which affect the output signal.
Innovation Solution
The design incorporates two sub-DACs that alternate through active-idle cycles, with one sub-DAC driving a load resistor and the other a dummy load resistor during orthogonal cycles, allowing internal bias points to be optimally set without parasitic capacitance charging or discharging, thereby maintaining maximum dynamic linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional current-steering type DACs change internal bias points to accommodate output values during switching transients, then the DAC can adapt to different output values, but parasitic capacitors charge or discharge in a non-linear way which compromises dynamic performance
Solution Approach 1:
The DAC is divided into two separate sub-DACs that operate in alternating active-idle cycles. This segmentation allows each sub-DAC to maintain stable bias points while collectively providing the full output range, resolving the contradiction between adaptability and dynamic performance.
Solution Approach 2:
The two sub-DACs operate in periodic active-idle cycles, with each sub-DAC being active for one cycle and idle for the next. During idle cycles, bias points can be optimized without affecting the output signal, while during active cycles, the other sub-DAC maintains the output. This periodic operation resolves the contradiction by separating the adaptation function from the signal production function in time.
2Speed
If internal bias points are forced to change during switching transients, then the DAC can transition between output values, but non-linear charging or discharging of parasitic capacitors affects the output signal
Solution Approach 1:
During idle cycles, each sub-DAC prepares its internal bias points and charges parasitic capacitors in advance before becoming active. This preliminary action ensures that when a sub-DAC becomes active, no significant charging or discharging occurs during the active cycle, eliminating non-linear effects in the output signal while maintaining fast switching response.
3Device complexity
If a single DAC structure is used, then the device complexity is lower, but the dynamic linearity cannot be maintained at maximum level
Solution Approach 1:
The DAC is segmented into two identical sub-DACs sharing common circuitry and operating in alternating cycles. This segmentation achieves maximum dynamic linearity by ensuring one sub-DAC is always in a stable, optimized state while the other handles transitions, without requiring a completely separate complex structure for each function.
Solution Approach 2:
Both sub-DACs are designed with identical structures and can perform both signal production and bias optimization functions. Each sub-DAC serves as both an active signal source and an idle optimization unit, allowing the system to achieve high dynamic linearity using replicated rather than fundamentally different circuit structures.
Data Source
AI summary
A current-steering type digital-to-analog converter (DAC) is disclosed. The DAC includes a first sub-DAC, a second sub-DAC and a controlling device. Both the first sub-DAC and the second sub-DAC are configured to receive input signals. The controlling device selectively and periodically sends output signals of either the first sub-DAC or the second sub-DAC to a resistive load while sending output signals of the remaining one of the two sub-DACs to a dummy resistive load. An output of the DAC is provided at the resistive load.