Current-Steering DAC Class AB Control for Low-Glitch Linearity
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Solution Overview
Problem
Current steering digital to analog converters (DACs) face issues with high current consumption in class A mode and distortion in class B mode due to transient glitches, which affect power efficiency and linearity.
Innovation Solution
Implementing a class AB mode operation that adjusts the proportion of unit cells operating in class A and class B modes, using a programmable AB_Factor to reduce transient glitches and non-linearity, and employing charge injection cancellation capacitors and low impedance bias schemes to mitigate distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all unit cells operate in class A mode, then linearity is maintained, but current consumption is high
Solution Approach 1:
The patent divides the unit cells into two groups: those operating in class A mode and those operating in class B mode. This segmentation allows different operational characteristics to be applied to different portions of the DAC, enabling linearity to be maintained where needed while reducing current consumption in other portions.
Solution Approach 2:
Different operational modes (class A and class B) are applied to different unit cells based on local requirements. The class A unit cells maintain high linearity for critical portions of the signal, while class B unit cells provide current reduction for less critical portions, achieving overall optimization.
2Use of energy by moving object
If unit cells operate in class B mode, then current consumption is reduced, but transient glitches and distortion occur
Solution Approach 1:
The patent converts the harmful transient glitches generated by class B operation into beneficial charge compensation events. By detecting the glitches and applying compensating charge through injection circuits, the harmful effects are transformed into useful corrections that improve overall signal quality.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the expected transient glitches before they affect the output. Charge injection circuits are configured to counteract the glitch effects in advance, preventing distortion before it occurs.
3Duration of action of moving object
If switches transition rapidly to reduce glitch duration, then transient effects are minimized, but switching losses increase
Solution Approach 1:
The patent changes the timing parameters of switch transitions to optimize the trade-off between glitch duration and switching losses. By carefully controlling the timing and duration of switch transitions, the patent minimizes both the glitch duration and the associated switching losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves a balance between linearity and power consumption by reducing the number of current sources in class B mode, minimizing glitches, and improving bias node recovery, thereby enhancing the overall performance of DACs.
Implementation Method 1
employing charge injection cancellation capacitors and low impedance bias schemes to mitigate distortion
Implementation Method 2
employing charge injection cancellation capacitors and low impedance bias schemes to mitigate distortion
Data Source
AI summary
Methods and apparatus to control current steering digital to analog converters are described herein. In one example, a digital to analog converter includes a first unit cell including a positive output and a negative output, wherein the positive output of the first unit cell and the negative output of the first unit cell comprise substantially equal magnitudes and wherein the positive and negative outputs of the first unit cell are substantially one hundred eighty degrees out of phase; and a second unit cell including a positive output and a negative output, wherein the positive output of the second unit cell is substantially zero when the negative output of the second unit cell is non-zero.


