Current-Steering DAC Channel Layout for Low-Noise Ramp Linearity
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Solution Overview
Problem
Current steering digital-to-analog converters suffer from mismatch between channels, leading to reduced linearity, increased noise, and longer settling times.
Innovation Solution
A digital-to-analog converter design featuring multiple channels with bias circuits, current cells, selection circuits, and switches, where selection signals control current flow through resistors or ground, reducing noise and settling time by maintaining capacitor charge during switch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current steering digital-to-analog converter uses multiple channels with direct bias node switching, then channel flexibility is improved, but linearity deteriorates due to mismatch between channels
Solution Approach 1:
The patent introduces a current cell as an intermediary component between the bias circuit and the output channel. The current cell converts the bias voltage into a controlled current that flows through a resistor to generate the ramp voltage. This intermediary structure isolates the bias node from direct switching operations, preventing mismatch between channels while maintaining the ability to control multiple channels independently through selection circuits.
2Speed
If bias nodes are switched directly in current steering DAC, then switching speed is improved, but noise increases and settling time lengthens
Solution Approach 1:
The current cell acts as a buffer between the bias voltage source and the switching network. By controlling current flow through the current cell rather than directly switching the bias node, the patent reduces switching noise and shortens settling time. The current cell's inherent current source characteristics provide stable current delivery during transitions, minimizing noise generation while maintaining fast response through the selection circuits.
Data Source
AI summary
A digital-to-analog converter includes a first channel configured to output a first ramp voltage through an output node, and a first bias circuit configured to apply a bias voltage to the first channel. The first channel comprises a plurality of current cells connected to the first bias circuit, a plurality of selection circuits and a plurality of switches, and a first resistor connected to the output node. Each of the plurality of selection circuits of the first channel comprises a first selection circuit configured to connect a current of one of the plurality of current cells to the first resistor in accordance with a first digital input signal, and a second selection circuit configured to connect the current of the current cell to one of the plurality of switches corresponding to the current cell in accordance with a second digital input signal complementary to the first digital input signal.