Current-Steering DAC Using Subthreshold Current Scaling
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Solution Overview
Problem
Current transistor-based digital-to-analog converters (DACs) face significant area challenges due to the need for constant scaling factors, leading to large transistor sizes and increased costs, especially in high-resolution applications where precise matching is required.
Innovation Solution
The use of field-effect transistors operated at sub-threshold voltages with degeneration resistors allows for identical transistor sizes across the array, modifying transconductance to achieve current scaling without the need for proportional area increases, enabling smaller and more efficient DACs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor-based current sources use constant scaling factors (e.g., factor of two) between current sources, then current precision and matching are improved, but the area occupied on the die increases significantly
Solution Approach 1:
The patent changes the operating parameter of transistors from strong inversion to sub-threshold region. In sub-threshold operation, transistors exhibit exponential current-voltage characteristics with a slope factor that can be controlled by device geometry. This allows current scaling to be achieved through aspect ratio adjustments rather than physical size scaling, resolving the contradiction between current matching precision and die area.
Solution Approach 2:
The patent applies different aspect ratios to different transistors in the current source array while keeping their physical dimensions similar. Each transistor's local aspect ratio is optimized to provide the required current scaling factor, allowing precise current control without proportionally increasing the area of each transistor. This local optimization resolves the area penalty associated with traditional scaling approaches.
2Manufacturing precision
If transistor sizes are increased to maintain constant scaling factors between current sources, then current ratio accuracy is improved, but the overall DAC size and manufacturing cost increase
Solution Approach 1:
By operating transistors in the sub-threshold region, the patent enables current ratio control through aspect ratio parameters rather than absolute size parameters. This parameter change allows high current ratio accuracy to be achieved with smaller, more uniform transistor sizes, reducing manufacturing complexity and cost while maintaining precision.
3Area of stationary object
If similar-sized transistors are used throughout the array, then area is reduced and manufacturing is simplified, but achieving precise current scaling ratios becomes more difficult
Solution Approach 1:
The patent exploits the sub-threshold slope factor as a controllable parameter to achieve current scaling with uniformly sized transistors. By adjusting the aspect ratio of similar-sized transistors, precise current scaling ratios are obtained without requiring large area variations between devices, thus resolving the contradiction between area reduction and scaling precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in physically smaller DACs with improved efficiency and reduced size penalties, maintaining high resolution while minimizing errors and area consumption.
Implementation Method 1
The transistors are operated at sub threshold gate-source voltages
Implementation Method 2
modifying transconductance to achieve current scaling without the need for proportional area increases
Implementation Method 3
an Nth transistor acting as a Nth current source has a degeneration resistor comprised of a first part that is only in a current flow path to the Nth transistor and has a value 2R and a second part which is in the current flow path with the Nth transistor and a further load that draws a current equal to the current passed by the Nth transistor and has a value of R+(XN−2)R
Implementation Method 4
each voltage modification device supplies current to a respective current generator and a subsequent voltage modification device and the transistors exhibit a change in an aspect ratio x between the transistors of the voltage modification devices and the current source transistors which is a function of a current division ratio D between stages
Data Source
AI summary
Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.