Current Switch Clock Loading for Low-Distortion DACs
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Solution Overview
Problem
Current current steering digital-to-analog converters (DACs) experience increased errors and noise with operating frequency, leading to harmonic distortion and signal-dependent clocking issues, which are not effectively addressed by existing solutions like the addition of dummy latches that increase complexity and power consumption.
Innovation Solution
Implementing a digital control circuitry with a SR latch configuration using NAND or NOR gates, which pre-charges input nodes to a consistent state, ensuring the clock driver sees a constant load and reducing third-order harmonic distortion by controlling switching elements with a clock-independent data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple current switching elements are clocked from the same clock buffer, then switching instant mismatch is minimized, but signal-dependent loading causes third order distortion
Solution Approach 1:
The invention segments the clocking function by providing separate clock buffers for different groups of switching elements. Instead of using a single clock buffer for all elements, the clocking function is divided into multiple independent buffers, each driving a specific subset of switches. This segmentation prevents the single buffer from experiencing signal-dependent loading variations that cause distortion, while still maintaining synchronized switching instants across all elements through coordinated clock distribution.
Solution Approach 2:
The invention introduces intermediate clock distribution circuitry between the clock source and the switching elements. These intermediate buffers act as mediators that isolate the clock source from signal-dependent loading variations. The intermediaries buffer and redistribute clock signals, ensuring that switching elements receive clean, consistent clock edges regardless of the instantaneous switching state of other elements, thereby eliminating third order distortion.
2Object-generated harmful factors
If dummy latches are added to equalize loading, then code dependent noise is reduced, but device complexity and power consumption increase
Solution Approach 1:
The invention extracts the load equalization function from the data path by using dedicated clock buffers that are independent of the data signals. Instead of modifying the data path with dummy latches, the solution removes the problematic coupling between data and clock loading by separating them into independent circuits. The clock buffers are designed to present consistent loading regardless of data state, effectively taking out the noise-generating interaction without adding complexity to the data processing path.
3Productivity
If operating frequency is increased, then conversion speed is improved, but errors and noise increase causing harmonic distortion
Solution Approach 1:
The invention introduces dynamic clock distribution that adapts to the instantaneous switching requirements of the DAC. The clocking system dynamically adjusts to balance the loading on each clock buffer based on which switching elements need to change state. This dynamic adaptation allows the system to operate at higher frequencies by ensuring that each clock buffer drives a manageable, balanced load, preventing the accumulation of errors and noise that would otherwise cause harmonic distortion at high speeds.
Data Source
AI summary
A system and method is provided for code independent switching in a digital-to-analog converter (DAC). A synchronous digital circuit is triggered by a synchronizing clocking signal and develops a digital data signal. A circuit arrangement provides the synchronizing clock a constant load at every clocking cycle, thereby assuring a data independent load. By providing a data independent load to the synchronizing clock at every clocking cycle, third harmonic distortion is advantageously reduced.