Current-Switching Cell With Half-Rate Retiming for Faster DACs
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Solution Overview
Problem
Conventional digital-to-analog converters face limitations in high-speed operation due to inaccuracies in retiming and waveform distortion caused by non-coincident switch driving timings, which restrict conversion speed and increase power consumption, especially when using interleaved methods that require multiple sub-converters and complex mixers.
Innovation Solution
A current-switching cell design that employs two latch circuits and a switch circuit with four switches, driven by half-rate signals and a select signal, allowing for retiming and current switching with reduced clock frequency requirements, enabling faster conversion speeds while maintaining low power consumption and high signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional current-switching cells with single latch circuits are used, then circuit complexity is reduced, but conversion speed is limited due to inaccurate retiming and non-coincident switch driving timings
Solution Approach 1:
The patent divides the retiming function into two separate latch circuits (first latch circuit and second latch circuit) that operate with different clock phases. This segmentation allows each latch to handle specific timing requirements independently, achieving coincident switch driving timings and enabling faster conversion speeds without excessive complexity increase.
Solution Approach 2:
The patent introduces dynamic clock phase switching through the select switch, which dynamically connects between the first latch circuit and second latch circuit based on clock phases. This dynamic operation allows the circuit to adapt to different timing requirements and achieve high-speed operation with proper retiming.
2Speed
If interleaved methods with multiple sub-converters are used, then conversion speed is increased, but power consumption increases and signal quality degrades
Solution Approach 1:
The patent merges the retiming and switching functions into a unified current-switching cell structure that uses two latch circuits working in coordination rather than separate sub-converters. This consolidation achieves high conversion speed while reducing power consumption by eliminating redundant circuitry required in interleaved architectures.
Solution Approach 2:
The patent changes the operational parameters by using half-rate clock signals with different phases to drive the two latch circuits, rather than using full-rate clocks in multiple parallel converters. This parameter change reduces the frequency requirements and associated power consumption while maintaining high conversion speed.
3Manufacturing precision
If conventional current-switching cells are used, then power consumption is reduced, but signal linearity degrades due to waveform distortion from non-coincident switch driving timings
Solution Approach 1:
The patent implements a feedback mechanism through the select switch that monitors clock phases and dynamically switches between the first and second latch circuits. This feedback control ensures that switches are driven at coincident timings, eliminating waveform distortion and improving signal linearity while managing circuit complexity.
4Speed
If higher clock frequencies are used to achieve faster conversion, then conversion speed increases, but power consumption and signal quality degradation increase
Solution Approach 1:
The patent uses periodic clock signals with different phases (first clock phase and second clock phase) to alternately drive the two latch circuits. This periodic action with half-rate frequencies achieves the required conversion speed while maintaining signal quality by ensuring proper retiming and coincident switch driving timings.
Data Source
AI summary
Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).