Current-Triggered Low Turn-On Voltage SCR for ESD Protection
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Solution Overview
Problem
Existing ESD protection solutions for integrated circuits introduce additional capacitance or leakage currents, failing to provide adequate voltage stress tolerance and efficient current handling at high-speed I/O buffers.
Innovation Solution
A current-triggered low turn-on voltage parasitic silicon controlled rectifier (SCR) is used, with a triggering mechanism involving an inverter, resistor, capacitor, and NMOS field effect transistor, isolating the trigger input from the I/O pad to minimize parasitic capacitance and leakage, and allowing low-voltage triggering of the SCR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a displacement current trigger SCR using AC currents that charge a capacitor is used for ESD protection, then the SCR can be triggered, but additional capacitance is introduced to the pad
Solution Approach 1:
The patent extracts the triggering function from the I/O pad by providing a separate trigger input that is electrically isolated from the pad through a reverse-biased diode. This separation removes the capacitance-associated triggering components from the pad structure, eliminating the source of additional parasitic capacitance while preserving ESD protection functionality.
Solution Approach 2:
The SCR structure is segmented into distinct functional regions: the anode connected to the I/O pad, a separate trigger input with its own doped region, and the cathode. This segmentation allows the trigger input to be isolated from the pad, enabling independent optimization of each component's electrical characteristics without compromising the other.
2Reliability
If an NMOS triggering transistor is used to activate the SCR, then the SCR can be triggered, but the NMOS transistor introduces leakage current and voltage stress limitations
Solution Approach 1:
The patent employs the inherent parasitic SCR structure that already exists within the semiconductor device as the protection mechanism. By utilizing the naturally occurring SCR and providing an external trigger input, the invention eliminates the need for separate NMOS triggering transistors, thereby removing the source of leakage current and voltage stress limitations associated with NMOS devices.
3Reliability
If existing ESD protection solutions are implemented, then ESD protection is provided, but additional capacitance or leakage currents are introduced, failing to provide adequate voltage stress tolerance
Solution Approach 1:
The patent introduces a reverse-biased diode as an intermediary between the I/O pad and the trigger input. This diode acts as an electrical barrier that isolates the trigger input from voltage spikes and stress on the pad, protecting the triggering mechanism from harmful voltage conditions while allowing the SCR to function effectively during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects integrated circuits from ESD with minimal parasitic capacitance, no additional NMOS devices, and high current handling capability, preventing voltage stress and maintaining electronic performance.
Implementation Method 1
the anode and the trigger input form a reverse-biased diode operative to isolate the triggering mechanism from the input/output pad when power is applied to the integrated circuit
Implementation Method 2
protecting integrated circuits from electrostatic discharge (ESD) and, more particularly, to the firing of a silicon controlled rectifier (SCR), operative to provide a safe discharge path for the ESD current
Data Source
AI summary
A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input/output pad when power is applied to the integrated circuit.