Curved Channel 3D Memory Device Cell Isolation
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Solution Overview
Problem
Current memory technologies face limitations in achieving high density, random access, and high operating speed in three-dimensionally stacked integrated circuit memory devices.
Innovation Solution
A vertical memory structure with curved channel structures is implemented, comprising alternating layers of insulating and word line materials, where recessed surfaces within the layers form convex or concave channels, and conductive pillars are used to create memory cells with dielectric charge trapping data storage, enabling efficient data storage and isolation between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally stacked NAND flash memory is used to achieve higher density, then storage capacity increases, but random access capability and operating speed deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D stacked architecture, organizing memory cells in three-dimensional space with alternating layers of insulating material and word line material. This dimensional change enables higher storage capacity while maintaining random access capability through the NOR configuration, where bit lines connect to multiple memory cells horizontally across different vertical layers.
Solution Approach 2:
The memory structure is segmented into multiple alternating layers of insulating material and word line material, with vertical openings creating distinct columnar segments. Each layer can be independently addressed through word lines, enabling random access to specific memory cells within the 3D stack. The segmentation into convex or concave channel structures further divides the channel region to improve cell isolation and reduce interference.
2Quantity of substance
If memory cells are closely packed to increase density, then storage capacity increases, but isolation between cells deteriorates causing disturbance
Solution Approach 1:
The patent applies different local structures to different regions of the memory cell. The channel structure is locally modified to be either convex or concave, creating regions of enhanced isolation between adjacent cells. The recessed inside surfaces of alternating layers provide localized geometric features that improve charge confinement and reduce electric field interference between neighboring memory cells, while maintaining high density through efficient space utilization.
3Speed
If conventional planar NOR flash memory is used to achieve random access and high speed, then operating speed improves, but storage density deteriorates
Solution Approach 1:
The invention extends the planar NOR flash memory architecture into the vertical dimension by stacking multiple alternating layers of insulating material and word line material. This 3D configuration maintains the random access capability of NOR memory through horizontal bit line connections across layers while multiplying storage density through vertical stacking. Memory cells are arranged in columns extending vertically, with each layer contributing additional storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory density and operating speed by providing better isolation and reduced disturbance between memory cells, while allowing for a high-density, random access NOR memory array with improved performance.
Implementation Method 1
The data storage structure including, for example, a dielectric charge trapping data storage structure, is disposed on the inside surfaces of the layers of word line material
Data Source
AI summary
A vertical memory structure comprises a stack of alternating layers of insulator material and word line material with a vertical opening through the alternating layers. One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening. First and second conductive pillars are disposed inside the vertical opening. A data storage structure is disposed on the inside surfaces of the layers of word line material, including on the recessed inside surfaces. A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening, and having first and second source/drain terminals at contacts with the first and second conductive pillars.