Curved Charge Storage Elements in 3D NAND Memory
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Solution Overview
Problem
Three-dimensional NAND memory devices with flat memory cells face challenges in optimizing the configuration of tunneling dielectrics with flat vertical surfaces, which affect the operational voltage and electrical field strengths.
Innovation Solution
The implementation of alternating stacks of electrically conductive strips and air gap strips over a substrate, with memory stack assemblies featuring two-dimensional arrays of lateral protrusion regions containing curved charge storage elements, enhancing electrical field strengths and reducing operational voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If flat vertical surfaces are used in tunneling dielectrics, then manufacturing simplicity is maintained, but electrical field strength is insufficient and operational voltage is high
Solution Approach 1:
The patent applies curvature to the tunneling dielectric surfaces by forming curved memory elements (arcs, segments, or full circles) instead of flat vertical surfaces. This curvature concentrates the electrical field in the tunneling dielectric region, enhancing field strength and enabling lower operational voltages. The curved geometry is achieved through specific deposition and etching processes that form arch-shaped or segment-shaped memory elements.
Solution Approach 2:
The patent transitions from two-dimensional flat memory cells to three-dimensional curved memory elements. By introducing curvature in the vertical and lateral dimensions, the tunneling dielectric thickness varies spatially, creating regions of enhanced electrical field strength. This dimensional change allows simultaneous optimization of field strength and voltage characteristics.
2Power
If curved memory elements are implemented, then electrical field strength is enhanced and operational voltage is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where sacrificial structures (such as mandrels or spacers) are formed first to define the curved geometry. The tunneling dielectric and charge storage layers are then deposited conformally on these pre-formed structures, automatically acquiring the curved shape. This preliminary structuring simplifies the overall manufacturing by avoiding complex direct patterning of curved surfaces.
Solution Approach 2:
The patent uses intermediary sacrificial structures (mandrels, spacers, or template layers) that mediate the formation of curved memory elements. These intermediaries are formed using standard planar processes, then used as templates to guide the deposition of curved layers, and finally removed or retained depending on the design. This intermediary approach bridges simple planar manufacturing and complex curved geometries.
3Productivity
If alternating stacks of conductive strips and air gap strips are used, then device integration density is improved, but structural complexity increases
Solution Approach 1:
The patent extracts the air gaps from the conventional filled structure, creating alternating stacks of conductive strips separated by air gap strips. This extraction of material (air instead of solid dielectric) reduces parasitic capacitance between adjacent conductive strips, improving signal integrity and enabling higher integration density. The air gaps are formed by selective removal of sacrificial materials or by direct deposition techniques.
Solution Approach 2:
The patent utilizes air gaps as porous/void spaces within the alternating stack structure. These air-filled regions serve as electrical isolators between conductive strips while occupying minimal space. The porous nature (air-filled voids) provides electrical insulation with lower dielectric constant than solid materials, reducing capacitive coupling and enabling tighter spacing of conductive elements for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical field strengths and reduces the required operational voltage for three-dimensional NAND memory devices, improving their performance and efficiency.
Implementation Method 1
each of the lateral protrusion regions comprises a respective curved charge storage element... enhancing electrical field strengths
Implementation Method 2
tunneling dielectrics have flat vertical surfaces... interfaces between a tunneling dielectric and the charge storage element
Data Source
AI summary
A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.