Curved Display Data Line Routing for Narrow Frame Width

The patent transitions from a two-dimensional planar routing to a three-dimensional stacked arrangement by placing data lines, circuit blocks, and pixel circuits in different layers (first through fourth sub-regions). This vertical stacking allows data lines to be routed through the curved frame area without increasing the horizontal frame width, as the routing occurs in the depth dimension rather than expanding the panel's external dimensions.

The patent implements a nested structure where circuit blocks are positioned between data lines and pixel circuits in a stacked configuration. The first circuit block is arranged between the first data line and the first pixel circuit, while the second circuit block is positioned between the second data line and the second pixel circuit. This nesting allows multiple functional elements to occupy overlapping spatial regions in different layers, enabling compact routing through the curved frame area without horizontal expansion.

The patent resolves the area expansion issue by arranging circuit blocks in the depth dimension through stacked sub-regions rather than spreading them horizontally across the curved frame area. The first and second circuit blocks are positioned in different layers (third and fourth sub-regions), allowing full driver circuit functionality to be implemented without increasing the curvature portion's horizontal width.

The patent employs a flexible stacked architecture where circuit blocks are arranged in thin, layered sub-regions that can be tightly packed within the curved frame area. This thin-film-like stacking approach allows the circuit blocks to conform to the curved geometry without requiring additional horizontal space, effectively providing driver circuit functionality within the constrained curvature portion.

The patent enables multiple data lines to be routed along the outer edge by stacking them in different layers (first and second sub-regions) rather than arranging them side-by-side horizontally. This vertical arrangement allows improved data signal distribution to multiple pixel circuits while maintaining a compact data line area width, as the multiple lines occupy the same horizontal footprint but different depth positions.

The patent merges multiple data routing functions into a compact stacked structure where the first data line and second data line are positioned in adjacent layers. This combining approach allows multiple data signals to be distributed efficiently through the curved frame area without requiring proportional increases in the data line area width, as the routing space is shared across layers rather than expanded horizontally.