Curved Edge Semiconductor Memory Device Isolation
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Solution Overview
Problem
In non-volatile memory devices, lattice damage during the plasma etching process for shallow trench isolation leads to a shallower tunnel insulating layer on active region edges, causing charge trapping and reducing the margin between write and erase threshold voltages, which degrades the device's reliability as design rules shrink.
Innovation Solution
A semiconductor device structure is formed with conductive lines crossing active regions, featuring a first oxide pattern on the lower sidewall of conductive patterns and a second oxide pattern on the device isolation insulating pattern, both with concavely curved top surfaces, and a second insulating layer between conductive patterns and the conductive line, to mitigate lattice damage and enhance edge insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a plasma etching process is performed to form a trench for device isolation, then the device isolation region is formed, but lattice damage occurs on the inner wall of the trench resulting in a shallower tunnel insulating layer on active region edges
Solution Approach 1:
The patent applies preliminary anti-action by performing a first oxidation process on the substrate before plasma etching to form an oxidized layer on the inner wall of the trench. This pre-formed oxidized layer prevents lattice damage during subsequent plasma etching, thereby maintaining uniform tunnel insulating layer thickness on active region edges despite the presence of device isolation structures.
Solution Approach 2:
The patent introduces an oxidized layer as an intermediary substance between the substrate and the plasma etching process. This intermediate layer acts as a protective barrier that mediates the harmful interaction between plasma etching and the substrate, preventing direct lattice damage while allowing the etching process to proceed for device isolation formation.
2Productivity
If design rule decreases to increase device density, then more devices can be integrated, but the tunnel insulating layer becomes shallower at active region edges leading to increased leakage current
Solution Approach 1:
The patent applies preliminary action by forming an oxidized layer on the substrate before trench formation and subsequent device fabrication. This pre-formed protective layer remains on active region edges throughout the manufacturing process, ensuring consistent tunnel insulating layer thickness even as design rules decrease and device density increases, thereby preventing edge-related leakage current.
3Productivity
If the space between control gate and substrate decreases to increase device density, then device integration improves, but leakage current increases due to reduced spacing
Solution Approach 1:
The patent applies local quality by selectively forming an oxidized layer only on specific regions of the substrate, particularly on active region edges and areas where leakage current is likely to occur. This localized oxidation provides enhanced insulation precisely where needed, allowing reduced spacing between control gate and substrate while maintaining low leakage current through improved local electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure reduces lattice damage, maintains a uniform tunnel insulating layer thickness, and increases the effective channel width, thereby improving the reliability and data retention capability of non-volatile memory devices by preventing leakage current and maintaining the margin between write and erase operations.
Implementation Method 1
a first oxide pattern disposed on a lower sidewall of the conductive patterns; a second oxide pattern that is in contact with the first oxide pattern and disposed on the device isolation insulating pattern
Data Source
AI summary
Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.