Curved Etch Stop Via Structure for Short-Resistant Interconnects
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Solution Overview
Problem
As semiconductor devices are scaled down, the narrow gaps between conductive lines increase the likelihood of electrical short circuits due to overlay errors and critical dimension errors in multilayer interconnecting structures, reducing the reliability of the devices.
Innovation Solution
A semiconductor device design featuring a first conductive line with a protrusion, an etch stop layer with a curved shape and thickness variation, and a via that avoids passing through the etch stop layer over the interlayer insulating layer, increasing the electrical short circuit margin by self-aligning the via to the conductive line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase integration, then device functionality and integration are improved, but the electrical short circuit margin is reduced due to narrow gaps between conductive lines and increased sensitivity to overlay and CD errors
Solution Approach 1:
The conductive line is formed with a protrusion that extends beyond the interlayer insulating layer surface before via formation. This preliminary structural preparation ensures that even if overlay or CD errors occur during subsequent via fabrication, the via will still contact the conductive line, thereby maintaining electrical connection reliability while preserving device integration benefits
Solution Approach 2:
The etch stop layer is designed with non-uniform thickness, being thicker at specific locations (such as above the interlayer insulating layer) and thinner at other locations. This localized thickness variation provides enhanced protection in critical areas where electrical short circuits are more likely to occur, while maintaining overall device integration
2Ease of manufacture
If overlay errors or critical dimension errors occur in multilayer interconnecting structures, then manufacturing complexity is reduced through standard lithography processes, but misalignment between via and conductive line increases leading to electrical short circuits
Solution Approach 1:
The conductive line protrusion is formed in advance during the interlayer insulating layer fabrication process, before via patterning and etching. This preliminary structure acts as a built-in alignment tolerance buffer, allowing standard lithography processes with inherent overlay and CD errors to still achieve reliable via-to-conductive line contact without requiring enhanced manufacturing precision
Solution Approach 2:
The protrusion structure creates a spatial buffer zone that compensates for potential misalignment. By extending the conductive line beyond the insulating layer boundary, the design provides a margin of error that cushions against overlay and CD variations, enabling use of conventional lithography processes while maintaining alignment accuracy
Data Source
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AI summary
A semiconductor device includes: a first interlayer insulating layer (10) disposed on a substrate; a first conductive line (Ma1) disposed in the first interlayer insulating layer (10) and having a protrusion protruding above an upper side of the first interlayer insulating layer (10); an etch stop layer (30) disposed on the first interlayer insulating layer (10) and the first conductive line (Ma1); and a via (50) passing through the etch stop layer (30) and contacting the first conductive line (Ma1), wherein the etch stop layer (30) includes a first etch stop layer (31) having a curved shape in a cross-sectional view and a second etch stop layer (32) disposed on the first etch stop layer (31) and having a thickness variation.