Curved Floating Gate for Non-Volatile Memory Program Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memory devices face challenges in enhancing program speed while minimizing interference phenomena, which affect cell distribution uniformity and lead to read failures due to increased overlapping areas between floating gates.
Innovation Solution
The non-volatile memory device features a floating gate with a lateral curve narrowing upwardly, increasing the overlapping area with the control gate while reducing adjacent floating gate interference by forming trenches in the isolation layers, thereby enhancing the coupling ratio and electrical distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the overlapping area between the control gate and the floating gate is increased to improve program speed, then the coupling ratio is improved, but the overlapping area between adjacent floating gates is increased causing interference phenomenon
Solution Approach 1:
The floating gate is designed with a curved lateral profile instead of a straight vertical profile. The floating gate extends further laterally at lower heights and tapers upward, creating a curved boundary that increases the overlapping area with the control gate while maintaining adequate spacing from adjacent floating gates. This curvature geometry resolves the contradiction by allowing improved coupling ratio without proportionally increasing interference between neighboring cells.
2Speed
If the second polysilicon layer is extended to increase the overlapping area, then the program speed is improved, but the distance between adjacent floating gates becomes smaller than the isolation layer width
Solution Approach 1:
The curved lateral profile of the floating gate allows the structure to extend outward in a controlled manner that increases the effective overlapping area with the control gate while the tapering upward portion maintains adequate vertical spacing from adjacent floating gates. This curved geometry enables the floating gate to achieve extended coverage without encroaching on the isolation layer spacing.
3Speed
If the floating gate width is increased to improve coupling ratio, then the program speed is enhanced, but the cell distribution uniformity deteriorates due to interference phenomenon
Solution Approach 1:
The curved lateral profile distributes the floating gate width increase in a graduated manner rather than uniformly, with greater extension at lower heights and tapering toward the top. This curved distribution pattern improves the coupling ratio while maintaining more uniform electrical characteristics across the cell array by reducing peak interference effects that would occur with uniform width expansion.
Data Source
AI summary
A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged vertically to the direction in which the isolation layers are arranged, a floating gate formed on the active region below the control gate and having a lateral curve so that the floating gate has a width narrowed upwardly, a gate insulating layer formed between the floating gate and the semiconductor substrate, and a dielectric layer formed between the floating gate and the control gate.