Curved-Gate MOS Transistor Layout for Higher Channel Width Density
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Solution Overview
Problem
Existing transistor designs face challenges in enhancing power density while maintaining device performance, particularly in increasing channel width without increasing the overall area of the MOS transistor.
Innovation Solution
A curved-gate transistor structure is proposed, featuring M*N semiconductor structural units arranged in an M*N array, with each unit having a curved gate region, source, and drain regions. The gate regions are connected in a diagonal design, and body contact regions are added near the source region to enhance latch-up resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the overlap area between the active region and the polysilicon is enlarged to increase the channel width, then the channel width increases, but the overall area of the MOS transistor increases
Solution Approach 1:
The gate structure is designed with a curved shape instead of a conventional straight or L-shaped configuration. The gate includes a first curved portion extending from the source region to the drain region, and a second curved portion extending from the drain region to the source region, forming a substantially circular or oval shape around the active region. This curvature allows the gate to enclose a larger channel width within a compact footprint, resolving the contradiction between increasing channel width and minimizing overall transistor area.
Solution Approach 2:
The gate structure transitions from a two-dimensional planar layout to a three-dimensional curved configuration. By extending the gate in multiple directions and curving it around the active region, the design effectively utilizes spatial dimensions to maximize channel width while maintaining a compact overall area. The gate wraps around the active region in a substantially circular pattern, achieving greater channel width without proportionally increasing the transistor footprint.
2Productivity
If the channel width is increased to improve device performance, then the saturation current increases, but the power density decreases due to increased area
Solution Approach 1:
The curved gate configuration allows the channel to follow a circular or oval path around the active region, effectively increasing the channel width and thus the saturation current without proportionally increasing the overall transistor area. This maintains high power density while achieving the desired current levels for improved device performance.
Solution Approach 2:
The first and second curved portions of the gate are merged to form a continuous, substantially circular gate structure that encloses the active region. This unified curved gate design maximizes the channel width within a compact area, simultaneously improving saturation current and maintaining power density by eliminating the need for separate gate segments that would increase the overall footprint.
3Ease of manufacture
If a conventional straight gate structure is used, then the manufacturing is simple, but the channel width is limited and power density cannot be improved
Solution Approach 1:
The curved gate structure can be manufactured using standard semiconductor fabrication processes by defining the gate pattern with appropriate photomask designs. The curvature is achieved through conventional lithography and etching techniques, making the manufacturing process relatively simple while enabling significantly increased channel width and improved power density compared to straight gate structures.
Solution Approach 2:
The gate geometry is changed from a straight linear configuration to a curved configuration with specific radius and curvature parameters. This parameter change in the gate shape allows the channel to follow a curved path, increasing the effective channel width within the same footprint area, thereby improving power density without complicating the manufacturing process beyond standard fabrication capabilities.
Data Source
AI summary
A curved-gate transistor structure, wherein gate regions of the curved-gate transistor structure are curved, wherein the curved-gate transistor structure comprises semiconductor structural units, each semiconductor structural unit further comprises body contact regions, the body contact regions and source region are on the same side of the gate region, each semiconductor structural unit further comprises a curved gate region; the body contact regions are added near the source region, and contact regions of each of the semiconductor structural units structure can easily form a network to enhance latch-up resistance; each of the first metal blocks can be connected to a same or different potential, and the two branches of the gate regions of the same semiconductor structural unit can also be connected to a same or different potential.