Curved Gate Channel Memory Cell Design
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Solution Overview
Problem
Existing memory cell technologies face challenges in achieving a stable structure and efficient process due to the complexity of static RAM and the slow access speed of dynamic RAM, particularly in preventing structural collapse and optimizing the coverage and control of gate channels.
Innovation Solution
The introduction of a memory cell design featuring a curved gate channel transistor with a buried bit line and word line, or a vertical gate channel transistor with a bit line and capacitor configuration, which simplifies the formation of doped regions and improves structural stability by allowing current flow in a downward direction, thereby preventing vertical structure collapse and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a vertical gate channel transistor is used, then the access speed is improved, but the structure may collapse
Solution Approach 1:
The patent employs a curved gate channel design where the channel transitions from a vertical configuration to a curved path. This curvature redistributes mechanical stresses along the channel, preventing the structural collapse that would occur with a purely vertical gate channel while maintaining the fast access speed benefits of the vertical orientation.
Solution Approach 2:
The curved gate channel is nested within a multi-layered structure comprising alternating conductive and insulating layers. This nested configuration provides mechanical support to the curved channel, enhancing structural stability while preserving the electrical performance and access speed characteristics.
2Speed
If a complex structure is used to improve performance, then the access speed is improved, but the manufacturing complexity increases
Solution Approach 1:
The gate channel is segmented into multiple sections with different orientations and curvatures. Each segment can be independently optimized for electrical performance while the overall segmented structure maintains manufacturability through standardized fabrication processes for each segment type.
Solution Approach 2:
The patent optimizes specific parameters of the curved gate channel including curvature radius, channel length, and doping concentration profiles. By carefully controlling these parameters, the design achieves high access speed while maintaining a structure that can be manufactured using existing semiconductor fabrication techniques.
3Ease of manufacture
If a curved gate channel is used, then the manufacturing process is simplified, but the word line coverage must be improved
Solution Approach 1:
The word line is extended into the third dimension by forming it as a three-dimensional structure that wraps around and follows the curvature of the gate channel. This dimensional extension ensures complete coverage of the curved channel surface, improving control and electrical contact while maintaining the manufacturing simplicity of the curved channel design.
Data Source
AI summary
A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.