3D Semiconductor Channel Structure With Curved Gate Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics are deteriorated due to high integration, leading to challenges in achieving excellent performance and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with active patterns, semiconductor patterns, source/drain patterns, and gate electrodes arranged in specific configurations, including curved surfaces and intersecting directions, along with metal layers and insulating layers to enhance electrical connections and surface areas, is proposed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOSFETs are scaled down to reduce device size, then device integration is improved, but operating characteristics are deteriorated
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertical channel structures. The gate electrode wraps around the semiconductor pattern in a FinFET or GAAFET configuration, creating a 3D active region that increases the effective channel area without increasing the device footprint, thereby maintaining scaling benefits while improving operating characteristics
Solution Approach 2:
The patent employs curved surface geometries in the semiconductor patterns, where the top surface includes curved portions that increase the surface area in contact with the gate electrode. This curvature approach maximizes the gate-controlled channel area within a compact footprint, improving current flow characteristics while maintaining small device dimensions
2Productivity
If device size is reduced for high integration, then productivity is improved, but electrical characteristics are deteriorated
Solution Approach 1:
By stacking multiple semiconductor patterns vertically to form multi-layer channel structures, the patent achieves higher integration density in the vertical dimension while each individual transistor maintains excellent electrical characteristics through improved gate control. This allows more devices per chip area without sacrificing performance
Solution Approach 2:
The patent implements nested structures where gate electrodes surround semiconductor patterns in concentric or layered configurations. The gate structure is positioned to wrap around or enclose the active channel regions, maximizing the gate-controlled surface area within a compact volume and improving carrier modulation efficiency
3Reliability
If semiconductor patterns have larger surface area in contact with gate electrodes, then current flow is improved, but device complexity increases
Solution Approach 1:
The semiconductor pattern top surface includes curved portions that naturally increase surface area without requiring complex multi-layer stacking. The curved geometry is achieved through standard lithography and etching processes, providing enhanced gate contact area while maintaining relatively simple device structure and fabrication
Solution Approach 2:
The patent applies curved surface geometry specifically to the top surface of the semiconductor pattern where gate contact occurs, while maintaining simpler geometries in other regions. This localized application of complexity optimizes the critical interface area without unnecessarily complicating the overall device structure or fabrication process
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a first semiconductor pattern on the active pattern, and gate electrodes extending in a first direction and arranged in a second direction intersecting the first direction. A first top surface of the first semiconductor pattern includes first and second corners spaced apart from each other in the first direction. The first top surface of the first semiconductor pattern includes a first portion connecting the first and second corners. A length of the first portion of the first semiconductor pattern is greater than a distance in the first direction between the first corner and the second corner.