Curved Gate Oxide Profile in Split Gate MOSFETs
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Solution Overview
Problem
Conventional manufacturing processes for split gate power MOSFETs face challenges in forming a uniform isolation layer, leading to sharp corners, increased overlap between gate-to-source and gate-to-drain capacitance, and reduced gate oxide breakdown due to correlated growth of the isolation and gate oxides.
Innovation Solution
A method where the poly-1 region is recess etched and sidewall oxide is removed, refilled with a dielectric material, and planarized to avoid sharp corners, allowing a curved dielectric profile and subsequent gate oxide formation, reducing overlap and enhancing breakdown reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the isolation layer is grown on the exposed poly-1 region simultaneously with gate oxide formation, then the manufacturing process is simplified, but sharp corners are formed and the isolation layer thickness cannot be increased to compensate for defects
Solution Approach 1:
The patent divides the isolation layer formation into two separate steps: first forming the isolation layer on the poly-1 region, then performing a recess etch to create a curved profile. This segmentation allows independent optimization of each step, avoiding the sharp corner problem while maintaining process simplicity.
Solution Approach 2:
The isolation layer is formed preliminarily before the gate oxide, allowing the isolation layer to be made thicker to compensate for defects. The recess etch is then performed to create the curved profile, ensuring that the isolation layer thickness can be optimized independently of the gate oxide thickness.
2Ease of manufacture
If the isolation layer conforms to the profile of the underlying poly-1 region, then the formation process is straightforward, but voids or defects on the poly-1 surface are translated into distorted oxide profiles
Solution Approach 1:
The isolation layer is formed preliminarily on the poly-1 region, and then a recess etch is performed to create a curved profile. This preliminary formation followed by selective removal eliminates the direct conformal relationship, preventing surface voids from being translated into distorted oxide profiles while maintaining ease of formation.
3Ease of manufacture
If the isolation layer and gate oxide are formed simultaneously with correlated thicknesses, then the process is simplified, but the isolation layer cannot be made thicker to compensate for defects
Solution Approach 1:
The patent segments the formation process into separate steps: first forming the isolation layer with sufficient thickness to compensate for defects, then performing a recess etch to create the curved profile. This segmentation decouples the thickness control of the isolation layer from the gate oxide, allowing independent optimization for reliability.
Solution Approach 2:
The isolation layer is formed preliminarily with the required thickness for defect compensation, and then the recess etch is performed to create the curved profile. This preliminary thick formation ensures that the isolation layer can compensate for defects while the subsequent etching creates the desired profile without reducing the thickness benefit.
4Ease of manufacture
If a sharp corner is formed where the isolation layer meets the trench sidewalls, then the manufacturing process is simpler, but the sharp corner retards gate oxide thickness and reduces breakdown reliability
Solution Approach 1:
The patent explicitly introduces a curved profile at the interface between the isolation layer and the trench sidewalls by performing a recess etch. This curvature eliminates sharp corners, preventing gate oxide retardation and improving breakdown reliability while adding minimal complexity to the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overlap between gate-to-source and gate-to-drain capacitance, fills defects in the poly-1 surface, and avoids gate oxide retardation, resulting in improved reliability and reduced on-resistance.
Implementation Method 1
a gate oxide layer formed over the curved boundary of the dielectric layer and the trench sidewalls
Implementation Method 2
refilled with a dielectric material
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.