Curved Gate Electrode Semiconductor Device Stress Alignment
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Solution Overview
Problem
Current semiconductor technologies fail to optimize the positional relationship between applied stress to the channel region and electron state in the vicinity of the source region, leading to ineffective improvements in transistor characteristics.
Innovation Solution
A semiconductor device and manufacturing method that position the peaks of the stress distribution between the pn junction boundaries of the channel region and the source and drain regions, ensuring overlap with the potential distribution peak near the source region, thereby enhancing carrier velocity and saturation current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If stress-introducing layers are formed on source and drain regions, then carrier mobility in the channel region is improved, but the positional relationship between stress distribution peak and electron state peak is not optimized
Solution Approach 1:
The gate electrode is formed before the source and drain regions in a gate-first process, allowing the stress-introducing layers to be positioned relative to the gate structure. This preliminary formation enables subsequent alignment of stress peaks with electron state peaks through controlled formation of extension regions and side-wall insulating films, resolving the positional alignment issue between stress distribution and carrier transport.
Solution Approach 2:
The patent applies different structures to different regions: stress-introducing layers are formed on source and drain regions with specific crystal orientations, while extension regions have tailored impurity concentrations. The side-wall insulating films are selectively formed on gate electrode side walls to control stress distribution locally. This localized structural differentiation enables precise control of stress-electron state alignment in the channel region.
2Reliability
If extension regions intrude into regions underneath gate electrode end portions, then short channel characteristics are improved, but stress distribution peak shifts outward away from electron state peak
Solution Approach 1:
The patent controls the impurity concentration parameters in extension regions to be lower than in source/drain regions, and adjusts the depth and lateral extent of extension region intrusion. By changing these parameters, the stress distribution profile is modified so that the stress peak aligns with the electron state peak in the channel, even when extension regions intrude underneath the gate electrode end portions to improve short channel characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier velocity and improves driving capability by maximizing the effect of applied stress on the channel region, benefiting both n-channel and p-channel type semiconductor devices.
Implementation Method 1
the characteristics of the transistors forming the circuit are improved by increasing carrier mobility through application of stress to the channel region using stressing film material
Data Source
AI summary
A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.