Curved Upper Interconnect Layout for Dense Logic Cell Routing
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high reliability and integration density while maintaining efficient manufacturing processes, particularly in the formation of interconnection lines that require multiple mask patterns due to tight spacing and optical proximity effects.
Innovation Solution
The semiconductor device incorporates a design with curved end lines for upper interconnection lines and concave/convex profiles, allowing for reduced spacing between adjacent interconnection lines and eliminating the need for additional mask patterns, thereby simplifying the fabrication process and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If straight interconnection lines are used with tight spacing, then integration density is improved, but manufacturing precision deteriorates due to optical proximity effects
Solution Approach 1:
The patent applies curvature to the end portions of interconnection lines, transforming straight lines into lines with curved ends. This curvature design allows the interconnection lines to maintain adequate spacing while achieving higher integration density, effectively resolving the conflict between tight spacing requirements and manufacturing precision limitations caused by optical proximity effects.
2Manufacturing precision
If additional mask patterns are added to ensure proper spacing, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The curvature of the interconnection line ends is designed in advance during the layout stage, before the actual fabrication process. This preliminary geometric design inherently ensures proper spacing between adjacent interconnection lines, eliminating the need for additional mask patterns or process steps to control spacing, thus reducing device complexity while maintaining manufacturing precision.
3Manufacturing precision
If curved end lines are used, then manufacturing precision is improved by reducing mask patterns, but device complexity increases due to design complexity
Solution Approach 1:
The curvature is applied only to the end portions of the interconnection lines rather than the entire length. This localized application of curvature maintains simplicity in the majority of the interconnection line design while achieving the spacing control benefits where needed, thus minimizing the increase in design complexity while improving manufacturing precision.
Data Source
AI summary
A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.