Curved Lateral Gate Transistor Layout for Lower Tunneling Oxide Stress
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Solution Overview
Problem
The stacked configuration of gates in semiconductor structures can lead to increased stress on the dielectric structure and tunneling oxide, causing deterioration and shorting, and requires high voltage differences for transistor operations, which reduces the structure's lifespan and increases the risk of failure.
Innovation Solution
A semiconductor structure with a lateral configuration of gates, featuring curved side surfaces and a dielectric structure between them, reduces stress on the tunneling oxide and allows for lower voltage differences during operations, improving coupling and reducing impedance, thereby enhancing the structure's reliability and lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a stacked configuration of gates is used in semiconductor structures, then the transistor can perform programming, read, and erase operations, but the stress on the dielectric structure and tunneling oxide increases causing deterioration and shorting
Solution Approach 1:
The patent inverts the conventional stacked gate configuration by placing gates in a lateral arrangement instead of vertical stacking. This inversion changes the stress distribution from concentrated vertical stress on thin dielectric layers to distributed lateral stress, eliminating the deterioration and shorting problems while maintaining full transistor operation capability for programming, reading, and erasing
Solution Approach 2:
The patent transitions from a vertical three-dimensional stacked gate structure to a lateral two-dimensional gate arrangement. This dimensional change allows the gates to be positioned side-by-side rather than stacked, reducing the height requirement and distributing electrical stress across a larger lateral area, thereby improving reliability while preserving functionality
2Adaptability or versatility
If a stacked configuration of gates is used, then transistor operations can be performed, but high voltage differences are required which increases the risk of failure
Solution Approach 1:
By inverting the gate configuration from stacked to lateral, the patent changes the electrical field distribution. The lateral arrangement allows voltage to be applied across longer paths with lower density, reducing the voltage difference required for each operational mode while maintaining effective control over the channel, thus reducing voltage stress and failure risk
3Ease of manufacture
If planar interfaces are used between gates, then the structure is simpler to manufacture, but the surface area of interfaces is reduced increasing impedance
Solution Approach 1:
The patent applies curved surfaces to the gate structures instead of planar interfaces. The curvature increases the effective surface area of the gate interfaces without complicating the manufacturing process, as the curved surfaces can be formed through standard deposition and etching techniques. This increased surface area reduces impedance while maintaining manufacturing simplicity
Data Source
AI summary
Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.