Curved Nanosheet Memory Architecture for Dense 3D Cell Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high memory cell density and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
The semiconductor device incorporates nano sheets with curved and tapered profiles, vertical and horizontal arrangements of conductive lines, and data storage elements, along with specific dielectric layers to form a three-dimensional structure that enhances memory cell integration and reduces capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory device structure is implemented, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies curved profiles to conductive lines (word lines and bit lines) instead of straight linear structures. The curved conductive lines follow arch-shaped paths that optimize the spatial distribution of electrical fields, reducing parasitic capacitance between adjacent lines while maintaining high memory cell density in the three-dimensional stacked configuration.
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional stacked memory cells with curved conductive lines extending in multiple spatial dimensions. This dimensional transformation allows for increased memory cell density through vertical stacking while the curved paths in the third dimension reduce parasitic capacitance by optimizing field distribution.
2Quantity of substance
If conventional linear conductive lines are used, then device complexity is low, but memory cell density is insufficient
Solution Approach 1:
The conductive lines are designed with curved arch profiles instead of straight lines, creating a more complex geometric configuration that enables optimized three-dimensional routing. This curvature allows the conductive lines to span greater horizontal distances while connecting vertical stacks, thereby increasing memory cell density without requiring additional interconnect layers.
Solution Approach 2:
The patent employs dynamic routing configurations where conductive lines follow curved paths that adapt to the three-dimensional memory cell arrangement. The curved conductive lines dynamically optimize their spatial configuration to maximize memory cell density while minimizing interference, representing a more sophisticated approach compared to static linear routing.
Data Source
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AI summary
A semiconductor device includes vertical and horizontal arrangements of nano sheets including curved sheets, tapered sheets, and horizontal sheets extending in a first horizontal direction between the curved sheets and the tapered sheets; a vertical arrangement of first conductive lines surrounding the horizontal sheets of the nano sheets in the horizontal arrangement and extending in a second horizontal direction; a horizontal arrangement of second conductive lines which are coupled in common to the curved sheets of the nano sheets in the vertical arrangement, extend in a vertical direction, and are respectively coupled to the curved sheets of the nano sheets in the horizontal arrangement; data storage elements coupled to the tapered sheets of the nano sheets in the vertical and horizontal arrangements; and an inter-cell horizontal dielectric layer including horizontal segments disposed between the first conductive lines in the vertical arrangement and vertical segments disposed between the second conductive lines in the horizontal arrangement.