Curved Nanosheet Memory Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high memory cell integration and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
A semiconductor device with nano sheets having curved and tapered profiles, surrounded by conductive lines and dielectric layers, along with data storage elements, is fabricated using a method that involves forming sheet stacks, spacers, and conductive lines to create a high-density, low-capacitance structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory structures are used, then memory capacity can be increased through stacking, but parasitic capacitance increases and integration density is limited
Solution Approach 1:
The patent applies curved profiles to nano sheets and conductive lines, replacing conventional straight or planar structures. The curved nano sheets and arched conductive lines reduce parasitic capacitance by increasing separation distance between adjacent conductive elements while maintaining compact footprint, thus improving integration density without the capacitance penalty of conventional stacked structures
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional curved and stacked architectures. By utilizing vertical stacking of curved nano sheets with horizontal and vertical conductive lines at multiple levels, the design achieves high integration density in the third dimension while managing parasitic effects through spatial separation
2Quantity of substance
If memory cells are miniaturized to increase density, then integration capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning and sacrificial layer techniques to pre-establish the curved nano sheet structures and conductive line positions before final assembly. By forming templates and guides in advance, the manufacturing process achieves high precision curved structures without requiring ultra-precise direct fabrication of the final miniaturized features
Solution Approach 2:
The patent uses nested structures where conductive lines are embedded within dielectric layers, and nano sheets are stacked within defined vertical spaces. This nesting approach allows miniaturization through compact spatial arrangement while maintaining manufacturability through hierarchical structuring that can be formed through sequential processing steps
Data Source
AI summary
A semiconductor device includes a nano sheet including a first sheet region, a third sheet region, and a second sheet region extending horizontally between the first and third sheet regions, the first region having a curved profile; a first conductive line surrounding the second sheet region of the nano sheet; a second conductive line coupled to the first sheet region of the nano sheet; and a data storage element coupled to the third sheet region of the nano sheet.