Curved Oxide Semiconductor Layer for Transistor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving favorable electrical characteristics, miniaturization, high integration, low power consumption, and data retention when power is stopped, particularly in transistors using oxide semiconductor layers.
Innovation Solution
A semiconductor device design featuring an oxide semiconductor layer with specific cross-sectional shapes and curvature radii in the channel width direction, along with a stacked structure of oxide semiconductor layers, to enhance electrical properties and integration, while maintaining low power consumption and data retention capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor layers are used for transistors, then electrical characteristics are improved, but device miniaturization and high integration are difficult to achieve
Solution Approach 1:
The patent applies dimensionality change by forming the oxide semiconductor layer with a curved cross-sectional shape (convex upward) rather than a flat shape. This three-dimensional structural modification allows the layer to maintain sufficient volume for good electrical characteristics while reducing the planar footprint, thereby enabling device miniaturization and higher integration density without sacrificing transistor performance
Solution Approach 2:
The patent changes the geometric parameters of the oxide semiconductor layer by controlling the curvature radius of its cross-section. By optimizing the curvature radius to be within a specific range (0.01 μm to 1 μm), the layer achieves both compact size for miniaturization and sufficient volume for favorable electrical characteristics, resolving the contradiction between performance and size
2Reliability
If oxide semiconductor layers are used for transistors, then electrical characteristics are improved, but power consumption increases
Solution Approach 1:
The patent changes the geometric parameters of the oxide semiconductor layer, specifically controlling the curvature radius of the cross-section to be within 0.01 μm to 1 μm. This parameter optimization reduces the required layer thickness and volume, which in turn reduces the capacitance and power consumption while maintaining favorable electrical characteristics through the optimized curved structure
3Reliability
If oxide semiconductor layers are used for transistors, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent employs dimensionality change by creating a curved cross-sectional structure of the oxide semiconductor layer that凸向上方 (convex upward). This three-dimensional configuration enhances data retention capabilities through improved charge storage characteristics while the curvature can be achieved through standard semiconductor fabrication processes, avoiding excessive device complexity
Data Source
AI summary
In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.