Curved Pad Interconnects for Passivation Integrity

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Solution Overview

Problem

In semiconductor device fabrication, the reliability of wire bonding pads is compromised due to metal corrosion during thermal cycles, leading to passivation stack destruction and moisture ingress, which affects the integrity and performance of the device.

Innovation Solution

A method of forming semiconductor devices with pad interconnects that lack 90° angles and angled structures, using a pad dielectric layer and conductive layer to create a pattern that enhances the integrity of the passivation layer, thereby reducing corrosion and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional pad interconnect patterns with 90° angles are used, then manufacturing is simpler, but the passivation layer integrity deteriorates during thermal cycles

Engineering Contradiction:
Improvepassivation layer integrityVSAvoidpad interconnect pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces conventional 90° angled pad interconnect patterns with curved or rounded patterns. This curvature eliminates the sharp corners that act as stress concentration points during thermal cycling, thereby preventing passivation layer destruction while maintaining manufacturability through standard photolithography processes.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If conventional pad patterns with sharp corners are used, then fabrication is easier, but corrosion resistance deteriorates due to moisture ingress

Engineering Contradiction:
Improvecorrosion resistanceVSAvoidpad pattern fabrication precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The curved pad interconnect patterns eliminate sharp corners that create stress concentrations and facilitate moisture ingress. The rounded geometry provides uniform stress distribution during thermal expansion and contraction, preventing passivation layer failure and reducing corrosion risk while remaining compatible with standard fabrication processes.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Reliability

If standard thermal cycle testing is performed on conventional devices, then reliability assessment is achieved, but device failure occurs due to passivation destruction

Engineering Contradiction:
Improvedevice reliability assessmentVSAvoidpassivation stack strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The curved pad interconnect design fundamentally changes the stress distribution pattern during thermal cycling. By eliminating 90° corners, the design prevents stress concentration that would otherwise cause passivation layer cracking and destruction, allowing devices to successfully pass standard thermal cycle reliability testing.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Data Source

PatentUS10777519B2Reliable passivation for integrated circuits
Publication Date: 2020.09.15 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US10777519B2 patent drawing
  • US10777519B2 patent drawing
  • US10777519B2 patent drawing

AI summary

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.