Curved PCB Layer Stack for CTE Mismatch Stress Relief
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Solution Overview
Problem
Current RF semiconductor chip packaging technologies, such as wafer level packages and embedded wafer level ball grid arrays, lack a material layer to buffer coefficient of thermal expansion (CTE) mismatch between the package and the printed circuit board (PCB), leading to reduced solder joint lifetime and increased reliability concerns, especially in high-frequency applications and automotive markets.
Innovation Solution
A printed circuit board with a layer stack comprising materials of different thermal expansion coefficients, configured to force the PCB into a curved shape, thereby unloading mechanical stress from interconnect structures and using a stiff low-RF-loss material for the first functional layer and a high CTE material for the second functional layer to achieve pre-warping, reducing the load on interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a short interconnection is used from the semiconductor chip device to the PCB, then RF transmission losses are reduced, but the solder joints are exposed to full CTE mismatch stress which reduces their lifetime
Solution Approach 1:
The PCB is pre-warped into a curved shape before mounting the semiconductor chip device. This preliminary action creates a pre-compression force that counteracts the tensile stress that will develop during thermal cycling, thereby protecting the solder joints from CTE mismatch damage while maintaining the short interconnection benefits
Solution Approach 2:
The layer stack is designed to generate a pre-compression force that acts in opposition to the expected thermal expansion stress. By applying this counteracting force before thermal cycling begins, the solder joints are protected from the full CTE mismatch stress that would otherwise occur during temperature variations
2Ease of manufacture
If the PCB is made flat and rigid, then manufacturing and assembly are simplified, but it cannot buffer CTE mismatch stress between package and PCB
Solution Approach 1:
The PCB's geometric parameter is changed from a flat shape to a curved/warped shape. This parameter change enables the PCB to buffer CTE mismatch stress through the pre-compression effect while still maintaining manufacturing feasibility through controlled layer stack design and material selection
Solution Approach 2:
A composite layer stack structure is implemented with multiple layers having different coefficients of thermal expansion. This composite structure generates the pre-compression force needed for CTE buffering while allowing the PCB to be manufactured using standard processes, thus maintaining ease of manufacture while improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly extends the lifetime of interconnect structures by reducing mechanical stress on solder joints and allows for reliable mounting of semiconductor chip devices across multiple thermal cycles, improving product reliability and longevity.
Implementation Method 1
the first layer includes a first material having a first coefficient of thermal expansion in a lateral direction and the second layer includes a second material having a second coefficient of thermal expansion in the lateral direction different from the first coefficient of thermal expansion such that the printed circuit board is forced by the layer stack into a curved shape
Data Source
AI summary
A printed circuit board for mounting at least one semiconductor chip device includes a metal structure provided in a first area of the printed circuit board for soldering the semiconductor chip device onto the metal structure. The printed circuit board includes a main surface, a layer stack including a first layer extending parallel to the main surface and a second layer extending parallel to the main surface. The first layer includes a first material having a first coefficient of thermal expansion in a lateral direction and the second layer includes a second material having a second coefficient of thermal expansion in the lateral direction such that the printed circuit board is forced by the layer stack into a curved shape at least in the first area of the printed circuit board.