Curved PCB Layout for Low-Inductance Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor devices experience increased inductance due to longer wire lengths and current paths when semiconductor chips are bonded to insulated circuit substrates via bonding wires.
Innovation Solution
A semiconductor device configuration featuring a printed circuit board with a curved section to reduce wire length and inductance, using connection members to connect semiconductor chips directly with lower-side wiring layers on the board, and a resin substrate for the insulated circuit substrate to allow flexible design of conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are bonded to insulated circuit substrate via bonding wires, then electrical connection is achieved, but wire length increases and inductance increases
Solution Approach 1:
The patent removes the bonding wire component from the electrical connection path. Instead of using bonding wires to connect semiconductor chips to the insulated circuit substrate, the invention directly bonds the chips to the substrate, extracting the unnecessary intermediary element that causes increased inductance and wire length.
Solution Approach 2:
The patent transitions from a three-dimensional wire-based connection (extending through space) to a planar surface-mounted connection. By arranging conductive patterns on the surface of the insulated circuit substrate and bonding chips directly to these patterns, the connection path is shortened from a vertical/wire-based dimension to a surface-level dimensional arrangement.
2Reliability
If bonding wires are used to connect semiconductor chips to terminals, then electrical connection is established, but current path length increases
Solution Approach 1:
The patent extracts and eliminates the bonding wire from the current path. By establishing direct bonding between semiconductor chips and the insulated circuit substrate's conductive patterns, the current path is shortened and the harmful intermediary (bonding wire) is removed from the electrical conduction route.
Solution Approach 2:
The patent merges the chip mounting function and electrical connection function into a single direct bonding process. Instead of separate wire bonding steps that extend the current path, the invention combines chip attachment and electrical connection into one integrated bonding operation, shortening the overall current path.
3Reliability
If conventional wiring structure is used, then electrical connection is achieved, but inductance increases
Solution Approach 1:
The patent extracts and removes the bonding wire element that generates parasitic inductance. By eliminating the wire-based connection and replacing it with direct chip-to-substrate bonding using surface conductive patterns, the source of harmful inductance is extracted from the system.
Solution Approach 2:
The patent changes the physical parameters of the electrical connection by transitioning from wire-based connections (with inherent inductance) to direct surface-mounted conductive patterns. This parameter change in the connection method fundamentally reduces the inductance value by altering the geometry and material composition of the current path.
Data Source
AI summary
A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.